User Guide

NPL-3 Company confidential
System Module and User Interface CCS Technical Documentation
Page 46 ãNokia Corporation. Issue 1 3/03
Frequency Synthesizers
The VCO frequency is locked by a PLL (phase locked loop) into a stable frequency source
given by a VCTCXO which is running at 26 MHz. The frequency of the VCTCXO is in turn
locked into the frequency of the base station with the help of an AFC voltage which is
generated in UEM by an 11 bit D/A converter. The PLL is located in Helgo and it is con-
trolled through the RFBus.
The required frequency dividers for modulator and demodulator mixers are integrated in Helgo.
Loop filter filters out the comparison pulses of the phase detector and generates a DC
control voltage to the VCO. The loop filter determines the step response of the PLL (set-
tling time) and contributes to the stability of the loop.
The frequency synthesizer is integrated in Helgo except for the VCTCXO, VCO, and the
loop filter.
Receiver
Each receiver path is a direct conversion linear receiver. From the antenna the received
RF-signal is fed to a front end module where a diplexer first divides the signal to two
separate paths according to the band of operation: either lower, GSM850 or upper,
GSM1800/1900 path.
Most of the receiver circuitry is included in Helgo.
Transmitter
The transmitter consists of two final frequency IQ-modulators and power amplifiers, for
the lower and upper bands separately, and a power control loop. The IQ-modulators are
integrated in Helgo, as well as the operational amplifiers of the power control loop. The
two power amplifiers are located in a single module with power detector. In the GMSK
mode the power is controlled by adjusting the DC bias levels of the power amplifiers.
Front End
The front end features include:
- Antenna 50 ohm input
- RX GSM1900 single output, RX GSM850/1800 balanced output
- TXs single 50 ohm input
-3 control lines from the Helgo