User Guide
Table Of Contents
- 10 - SCHEMATICS
- Table of Contents
- Title: Top level schematic
- Title: Top sheet (2)
- Title: DCT4 Common Baseband Schematic (Top level 2)
- Title: 5 pin Production Test Pattern
- Title: RF top sheet schematic
- Title: Mjoelner
- Title: Power amplifier
- Title: BB RF interface components
- Title: DCT4 common BB Schematic (top level)
- Title: RH-4 System connector
- Title: GSM RF BB interface
- Title: RH-4 Audio
- Title: MultiGND symbol bypass
- Title: GENIO and GPIO connection block
- Title: Rohm IR module 1.8V
- Title: Testpoints based Ostrich interface
- Title: Test and emulator interface
- Title: SIM reader
- Title: Testpoints for JTAG emulator
- Title: DC/DC convertor
- Title: RH-4 User interface
- Title: Discrete power management
- Title: Light filtering
- Title: Old power discrete users
- Title: UPP 8M implementation
- Title: Combo memory 128 +8 Mbit
- Title: Discrete decoupling capacitors for UPP
- Title: Discrete capacitors for memory without VFlash 1
- Title: Empty wing sheet
- BACK TO MAIN PAGE

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FOR RF POWER AMPLIFIER
RFICCNTRL/RFICCNTR_O
2: BU_AFC
0: RFBUSCLK
RFCONV/RFCONV_O: 0: RXIP
1: RXIM
2: RXQP
3: RXQM
4: TXIP
5: TXIM
6: TXQP
7: TXQM
GENIO/GENIO_O
9: RESETX_BIF
5: TXP
6: RESETX_MJOEL
9: VREFRF01
0: TXCRFAUXCONV/RFAUXCONV_O
2: RFBUSEN1
(see UEM sheet)
1: RFBUSDA
CONSTANT CURRENT SET RESISTOR
220k
R424
1
2
0
1
5
6
J424
0
J422
0
9
1
2
3
4
5
6
7
8
J423
7
8
0
1
2
J421
0
9
1
2
3
4
5
6
1n0
C426
GND
1k0
R420
0
1
2
R426
0
1
5
6
100R
10
11
12
13
5
6
7
8
9
10
11
12
GND
13
5
6
7
8
9
27k
0
1
2
GND
ISET
R422
C420
100p
GENIO(31:0)
RFCLK
RFCONV(9:0) RFCONV_O(9:0)
SLOWAD(6:0)
RFCLK_I
RFCLKGND_I
RFAUX(1:0)
RFICCTRL_O(2:0)RFICCTRL(2:0)
PUSL(3:0)
GENIO_O(31:0)
RFAUX_O(1:0)
RFCLKGND
LPRFCLK
LPRFCLK_I
RFAUXCONV_O(2:0)RFAUXCONV(2:0)
SLOWAD_O(6:0)
PUSL_O(3:0)
RFCONV_ANA_O(16:0)
RFCONV_DIGI_O(16:0)
RFCONV_ANA(16:0)
RFCONV_DIGI(16:0)










