User Guide

PAMS
Technical Documentation
NME–3
Technical Information
Page 28
Issue 1 10/99
– DSP memory
– BUSC (Bus Controller for controlling accesses from ARM to API, System
logic and MCU externel Memory, both 8– and 16 bit memories)
– System Logic
– CTSI (Clock, Timing, Sleep and Interrpt control)
t
WSHL
Figure 9. Write cycle timing.
RFIClk
RFIWrX
RFIDA(11:0)
RFIAD(3:0)
t
WSLH
t
WDSU
t
WDHD
t
WAHD
t
WASU
Table 12. Write Cycle Timing Characteristics
Parameter Symbol Min Max unit
Write strobe active delay time tWSHL 20 tcyc–20 ns
Write strobe inactive delay time tWSLH 20 tcyc–20 ns
Address bus set up time tWASU 30 ns
Address bus hold time tWAHD 30 ns
Data bus set up time tWDSU 30 ns
Data bus hold time tWDHD 30 ns
CCONT for CD949
The heart of the power distrubution is the CCONT. It includes all the
voltage regulators and feeds the power to the whole system. The
baseband digital parts are powered from the VBB regulator which
provides 2.8V baseband supply. The baseband regulator is active always
when the phone is powered on. The VBB baseband regulator feeds MAD
and memories plus COBBA digital parts. There is a separate regulator for
a SIM card. The regulator is selectable between 3V and 5V and controlled
by the SIMPwr line from MAD to CCONT. The COBBA analog parts are
powered from a dedicated 2.8V supply VCOBBA. The CCONT contains a
real time clock function, which is powered from a RTC backup when the
power supply is disconnected.