User Guide

6015/6015i/6016i/6019i (RH-55), 6012 (RM-20)
System Module Nokia Customer Care
Page 16 ©2004 Nokia Corporation Company Confidential Issue 1 - Revision 002 09/2004
UPP
The phone uses a UPP8Mv4.1/4.2 ASIC with 8Mbit of RAM. The UPP ASIC is designed to
operate in a DCT4 engine, and is designed as part of the DCT4 common baseband task
force. The DCT4 processor architecture consists of both DSP and MCU processors.
Blocks
UPP is internally partitioned into two main parts: the Brain and the Body.
The Brain consists of the Processor and Memory System (i.e., Processor cores, Mega-cells,
internal memories, peripherals, and external memory interface). The following blocks are
included: the DSP Subsystem (DSPSS), the MCU Subsystem (MCUSS), the emulation
control EMUCtl, the program/data RAM PDRAM, and the Brain Peripherals–subsystem
(BrainPer).
The Body consists of the NMP custom cellular logic functions. These contain all
interfaces and functions needed for interfacing with other DCT4 baseband and RF parts.
It includes the following sub-blocks: MFI, SCU, CTSI, RxModem, AccIF, UIF, Coder,
GPRSCip, BodyIF, SIMIF, PUP, and CDMA (Corona).
Memory
Following is a summary of the memory associated with the phones:
Synth LE UPP Synth IC
“1” 1.38 1.88
V
Load enable for
synth IC
“0” 0 0.4
Current 50 uA
Load resistance 10 kohm
Load capacity 20 pF
Table 10: Memory Summary
Model Type Memory Frequency (MHz)
6012 RM-20 Discrete
Flash: 64 Mb
SRAM: 4 Mb
800
6015 RH-55 Discrete
Flash: 64 Mb
SRAM: 4 Mb
800/1900
6015i RH-55 Combo
Flash: 64 Mb
SRAM: 16 Mb
800/1900
Table 9: RFIC Control (Continued)
Signal
Name
From To Parameter
Input Characteristics
Function
Min Type Max Unit