User Guide

Clocking scheme
In BB5.0, two main clocks are provided to the system: 38.4MHz RF clock produced by VCTCXO in RF section
and 32.768kHz sleep clock produced by RETU with an external crystal.
SMPS Clk is 2.4MHz clock line from RAPGSM to Tahvo used for switch mode regulator synchronizing in active
mode. In deep sleep mode, when VCTCXO is off, this signal is set to '0'-state.
BT Clk is 38.4MHz signal from Ahne ASIC to BT module.
Figure 70 Clocking scheme
Bluetooth
Bluetooth provides a fully digital link for communication between a master unit and one or more slave units.
The system provides a radio link that offers a high degree of flexibility to support various applications and
product scenarios. Data and control interface for a low power RF module is provided. Data rate is regulated
between the master and the slave.
The device Bluetooth is based on BC4 ROM1.0RDL BT chip.
USB
USB (Universal Serial Bus) provides a wired connectivity between host PC and peripheral devices.
USB is a differential serial bus for USB devices. USB controller (RAPGSM) supports USB specification revision
2.0 with full speed USB (12 Mbps). The device is connected to the USB host through the Pop-Port connector.
The USB bus is hot plugged capable, which means that USB devices may be plugged in/out at any time.
Accelerometer
Accelerometer can detect acceleration that is caused by speed change. It also detects acceleration that is
caused by Earth.
Accelerometer is used for implementing pedometer and tapping commands.
Accelerometer is controlled via an I2C bus. Acceleration data is transferred via the I2C bus.
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