PAMS Technical Documentation NSM–5 Series Transceivers System Module Issue 1 02/2002 Nokia Corporation
NSM–5 System Module PAMS Technical Documentation CONTENTS Transceiver NSM–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAMS Technical Documentation Work Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Memory Requirements . . . . . . . . . . . . . . . . . . . . . . MCU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COBBA GJP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NSM–5 System Module PAMS Technical Documentation Schematic Diagrams: DF7 layout 05 & 06 (A3 pages at the back of the binder) RF & BB (Version 0600 Edit 9) for layout version 05 & 06 . . . A–1 RF (Version 0600 Edit 20) for layout version 05 & 06 . . . . . . . A–2 BB Block Connections (Version 0600 Edit 7) for layout version 05 & 06 A–3 UI (Version 0600 Edit 23) for layout version 05 & 06 . . . . . . . .
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NSM–5 System Module PAMS Technical Documentation Transceiver NSM–5 Introduction The NSM–5 is a dual band transceiver unit designed for the GSM900 (including EGSM) and GSM1800 networks. It is both GSM900 phase 2 power class 4 transceiver (2W) and GSM1800 power class 1 (1W) transceiver. The transceiver consists of System/RF module (DF7), Display module (UX7) and assembly parts. The transceiver has a full graphic display and the user interface is based on a Jack style UI with two soft keys.
NSM–5 System Module PAMS Technical Documentation Interconnection Diagram LCD module Keyboard module 14 9 6 4 SIM Battery Radio Module 2 2 Issue 1 02/2002 Charger DF7 Antenna Microphone 2+2 3 IR Link Nokia Corporation 2 Earpiece 4 HF/HS Page 7
NSM–5 System Module PAMS Technical Documentation System Module Baseband Module The baseband architecture supports a power saving function called ”sleep mode”. This sleep mode shuts off the VCTCXO, which is used as system clock source for both RF and baseband. During the sleep mode the system runs from a 32 kHz crystal. The phone is waken up by a timer running from this 32 kHz clock supply. The sleeping time is determined by some network parameters.
PAMS Technical Documentation NSM–5 System Module Technical Summary The baseband module consists four ASICs; CHAPS, CCONT, COBBA– GJP and MAD2WD1, which take care of the baseband functions of the engine. The baseband is running from a 2.8V power rail, which is supplied by a power controlling ASIC CCONT. In the CCONT there are 6 individually controlled regulator outputs for RF–section and two outputs for the baseband. In addition there is one +5V power supply output (V5V).
NSM–5 System Module PAMS Technical Documentation External and Internal Signals and Connections This section describes the external electrical connection and interface levels on the baseband. The electrical interface specifications are collected into tables that covers a connector or a defined interface. DC (charger) connector DC (charger) connector is physically integrated in the same component with the accessory interface connector. DC connector has both jack and contact pads for desk stand.
NSM–5 System Module PAMS Technical Documentation Name Min BTEMP Typ Max Unit Notes 0 1.4 V Battery temperature indication Phone has a 100k (+–5%) pullup resistor, Battery package has a NTC pulldown resistor: 47k+–5%@+25C , B=4050+–3% 2.1 3 V Phone power up by battery (input) 20 ms Power up pulse width 2.85 V Battery power up by phone (output) 200 ms Power up pulse width 0 1 kohm Local mode initialization (in production) 0 0 V Battery ground 5 10 1.
NSM–5 System Module PAMS Technical Documentation Power Distribution In normal operation the baseband is powered from the phone‘s battery. The battery consists of one Lithium–Ion cell. An external charger can be used for recharging the battery and supplying power to the phone. The baseband contains parts that control power distribution to whole phone excluding those parts that use continuous battery supply. The battery feeds power directly to the CCONT and UI (buzzer and display and keyboard lights).
NSM–5 System Module PAMS Technical Documentation MAD LIM VOUT RSENSE 2A 1u 30V 100k ICHAR VIN VCH GND PWM VBAT CHARGER TRANSCEIVER CHAPS 0R22 22k PWM_OUT MAD CCONTINT VCHAR CCONT 1n 10k GND L_GND Startup Charging When a charger is connected, the CHAPS is supplying a startup current minimum of 130mA to the phone. The startup current provides initial charging to a phone with an empty battery. Startup circuit charges the battery until the battery voltage level is reaches 3.0V (+/– 0.
NSM–5 System Module PAMS Technical Documentation The voltage limit (VLIM1 or VLIM2) is selected by logic LOW or logic HIGH on the CHAPS (N101) VLIM input pin. In NSM–5 VLIM is fixed low in HW. When the switch in output overvoltage situation has once turned OFF, it stays OFF until the the battery voltage falls below VLIM and PWM = LOW is detected. The switch can be turned on again by setting PWM = HIGH.
NSM–5 System Module PAMS Technical Documentation Battery Removal During Charging Output overvoltage protection is also needed in case the main battery is removed when charger connected or charger is connected before the battery is connected to the phone. With a charger connected, if VOUT exceeds VLIM, CHAPS turns switch OFF until the charger input has sunken below Vpor (nominal 3.0V, maximum 3.4V). MCU software will stop the charging (turn off PWM) when it detects that battery has been removed.
NSM–5 System Module PAMS Technical Documentation PWM When a charger is used, the power switch is turned ON and OFF by the PWM input. PWM rate is 1Hz. When PWM is HIGH, the switch is ON and the output current Iout = charger current – CHAPS supply current. When PWM is LOW, the switch is OFF and the output current Iout = 0. To prevent the switching transients inducing noise in audio circuitry of the phone soft switching is used.
NSM–5 System Module PAMS Technical Documentation Vcc 0.85 0.05 Vcc 0.55 0.05 Vcc SIMCARDDETX SIGOUT GND Battery Temperature The battery temperature is measured with a NTC inside the battery pack. The BTEMP line inside transceiver has a 100k pullup to VREF. The MCU can calculate the battery temperature by reading the BTEMP line DC– voltage level with a CCONT (N100) A/D–converter. Pin Name Min 3 BTEMP Max Unit Notes 0 1.
NSM–5 System Module PAMS Technical Documentation Supply Voltage Regulators The heart of the power distrubution is the CCONT. It includes all the voltage regulators and feeds the power to the whole system. The baseband digital parts are powered from the VBB regulator which provides 2.8V baseband supply. The baseband regulator is active always when the phone is powered on. The VBB baseband regulator feeds MAD and memories, COBBA digital parts and the LCD driver in the UI section.
NSM–5 System Module PAMS Technical Documentation Switched Mode Supply VSIM There is a switched mode supply for SIM–interface. SIM voltage is selected via serial IO. The 5V SMR can be switched on independently of the SIM voltage selection, but can’t be switched off when VSIM voltage value is set to 5V. NOTE: VSIM and V5V can give together a total of 30mA. In the next figure the principle of the SMR / VSIM–functions is shown.
NSM–5 System Module PAMS Technical Documentation CCONT’s digital parts is released when the operating voltage is stabilized ( 50 us from switching on the voltages). Operating voltage for VCXO is also switched on. The counter in CCONT digital section will keep MAD in reset for 62 ms (PURX) to make sure that the clock provided by VCXO is stable. After this delay MAD reset is relased, and VCXO –control (SLEEPX) is given to MAD.
PAMS Technical Documentation NSM–5 System Module SLEEPX PURX CCPURX PWRONX VR1,VR6 VBB (2.8V) Vchar 1 2 3 1:Power switch pressed ==> Digital voltages on in CCONT (VBB) 2: CCONT digital reset released. VCXO turned on 3: 62 ms delay to see if power switch is still pressed. Power Up by RTC RTC (internal in CCONT) can power the phone up by changing RTCPwr to logical 1. Power Up by IBI IBI can power CCONT up by giving a short pulse (10ms) through the BTEMP line.
NSM–5 System Module 4. PAMS Technical Documentation Setting the real time clock to power off the phone by a timer. The RTC generates an interrupt signal, when the alarm is gone off. The RTC interrupt signal is connected to the PWRONX line to give a power off signal to the CCONT just like the power key. The power down is controlled by the MAD.
PAMS Technical Documentation NSM–5 System Module If the battery pack is disconnect during the sleep mode, the CCONT pulls the SIM interface lines low as there is no time to wake up the MCU. Charging Charging can be performed in any operating mode.The battery type/size is indicated by a resistor inside the battery pack. The resistor value corresponds to a specific battery capacity.
NSM–5 System Module PAMS Technical Documentation Audio control PCM serial interface The interface consists of following signals: a PCM codec master clock (PCMDClk), a frame synchronization signal to DSP (PCMSClk), a codec transmit data line (PCMTX) and a codec receive data line (PCMRX). The COBBA–GJP generates the PCMDClk clock, which is supplied to DSP SIO. The COBBA–GJP also generates the PCMSClk signal to DSP by dividing the PCMDClk. The PCMDClk frequency is 1.
PAMS Technical Documentation NSM–5 System Module Digital Control The baseband functions are controlled by the MAD asic, which consists of a MCU, a system ASIC and a DSP. MAD2 WD1 MAD2 WD1 contains following building blocks: – ARM RISC processor with both 16–bit instruction set (THUMB mode) and 32–bit instruction set (ARM mode) – TI Lead DSP core with peripherials: – API (Arm Port Interface memory) for MCU–DSP communication, DSP code download, MCU interrupt handling vectors (in DSP RAM) and DSP booting.
NSM–5 System Module PAMS Technical Documentation used for the sleep mode timing. The sleep clock is active when there is a battery voltage available i.e. always when the battery is connected.
NSM–5 System Module PAMS Technical Documentation Ball Name Pin Type Connected to/from Drive req.
NSM–5 System Module PAMS Technical Documentation Ball Name H1 VCC_IO L4 MCUAd7 O MCU MEMORY 2 0 MCU address bus L3 MCUAd8 O MCU MEMORY 2 0 MCU address bus L2 MCUAd9 O MCU MEMORY 2 0 MCU address bus K5 MCUAd10 O MCU MEMORY 2 0 MCU address bus J4 GND K3 MCUAd11 O MCU MEMORY 2 0 MCU address bus K2 MCUAd12 O MCU MEMORY 2 0 MCU address bus K1 MCUAd13 O MCU MEMORY 2 0 MCU address bus J3 MCUAd14 O MCU MEMORY 2 0 MCU address bus J2 MCUAd15 O MCU MEM
NSM–5 System Module PAMS Technical Documentation Ball Name Pin Type Connected to/from Drive req.
NSM–5 System Module PAMS Technical Documentation Ball Name J10 SCGND D9 BuzzPWM D11 LEADVCC G12 VibraPWM C9 GND E12 MCUGenIO3 I/O 2 Input, pullup pullup PR1001 General purpose I/O port E13 MCUGenIO2 I/O 2 Input, pullup pullup PR1001 General purpose I/O port J13 KBLights O 2 1 C5 AccTxData I/O 4 Tri– State external pullup Accessory TX data, Flash_TX B6 VCC_IO IO VCC in 3325c10 Power F11 HookDet I Input Non–MBUS accessory connection detector F10 HeadDet I In
NSM–5 System Module PAMS Technical Documentation Ball Name Pin Type Connected to/from Drive req.
NSM–5 System Module PAMS Technical Documentation Ball Name Pin Type Connected to/from Drive req.
NSM–5 System Module PAMS Technical Documentation Memories MAD memory configuration The MAD2WD1 used in NSM–5 contains 16 kW RAM, and 80 kW ROM memory. Memory The MCU program code resides in an external flash program memory, which size is 32Mbits (2048k x 16bit). The MCU work (data) memory size is 4096 kbits (512k x 16bit). Flash and SRAM memory chips are packed in same combo memory package.
NSM–5 System Module PAMS Technical Documentation 8–bit/16–bit databus. The BUSC bus controller supports 8– and 16–bit access for byte, double byte, word and double word data. Access wait states (0, 1 or 2) and used databus width can be selected separately for each memory block. Flash Programming The phone have to be connected to the flash loading adapter so that supply voltage for the phone and data transmission lines can be supplied from/to the adapter.
PAMS Technical Documentation NSM–5 System Module Flash Programming Sequence CCONT pin (PurX) MAD pin (FCLK (MBUS)) MAD pin 109 (FRX (FRxData)) MAD pin (FTX (FTxData)) SRAM D221 (Chip Sel) FLASH D210 (Chip Sel) CCONT pin (PurX) MAD pin (FCLK (MBUS)) MAD pin (FRX (FRxData)) MAD pin (FTX (FTxData)) Issue 1 02/2002 Nokia Corporation Page 35
NSM–5 System Module PAMS Technical Documentation COBBA GJP COBBA GJP ASIC provides an interface between the baseband and the RF–circuitry. COBBA performs analogue to digital conversion of the receive signal. For transmit path COBBA performs digital to analogue conversion of the transmit amplifier power control ramp and the in–phase and quadrature signals. A slow speed digital to analogue converter will provide automatic frequency control (AFC).
NSM–5 System Module PAMS Technical Documentation RF Module This RF module takes care of all RF functions of EGSM/DCS1800 dualband engine. RF circuitry is located on one side of the 8 layer tranceiver– PWB. PWB area for the RF circuitry is about 15 cm2. The RF design is based on the first dualband direct conversion RF–IC ”Hagar”. So there is no intermediate frequency and that means the number of component is much lover than before and there shall be much less interference problems than previously.
NSM–5 System Module PAMS Technical Documentation RF Frequency Plan HAGAR 925–960 MHz I–signal Q–signal 1805–1880 MHz f f/2 RX f f/2 f f/2 PLL 3420– 3840 MHz f f/2 26 MHz VCTCXO 880–915 MHz I–signal Q–signal 1710–1785 MHz TX DC characteristics Regulators Transceiver has a multi function power management IC at baseband section, which contains among other functions, also 7 pcs of 2.8 V regulators. All regulators can be controlled individually with 2.
VBATT 1.76 A PA Vpc (Hagar) VXOENA SYNPWR Nokia Corporation VR 1 vxo VR 2 vrx VR VR VR 3 4 5 vsyn_1 vsyn_2 vtx VR 6 20 mA LNA V5V 4.7V Reg HAGAR bias ref COBBA analog VCTCXO +buff. VREF vref_2 6 mA 2 mA VR 7 PAMS Technical Documentation BATTERY Power Distribution Diagram Issue 1 02/2002 3.9 V 20 mA Page 39 1.3 mA VCO RX: 18.5 mA TX: 31.5 mA 67 mA HAGAR RF–IC RX / TX parts PLL 1.6 mA TXC TXP NSM–5 System Module RX: 26 mA TX: 29 mA 7.
NSM–5 System Module PAMS Technical Documentation RF Functional Description TXIP TXIN TXQP TXQN TXP 26 MHz f f/2 f/2 f EGSM dual PA buffer SAW Diplexer PCN f/2 HAGAR f/2 f f f/2 f PLL BIAS TXC VCXO AFC 13 MHz to ASIC SHF VCO SERIAL CTRL BUS VREF_2 1.5 V RXREF 1.2 V I Q Architecture contains one RF–IC, dualband PA module, VCO–module, VCTCXO module and discrete LNA stages for both receive bands.
NSM–5 System Module PAMS Technical Documentation Frequency synthesizer VCO frequency is locked with PLL into stable frequency source, which is a VCTCXO–module ( voltage controlled temperature compensated crystal oscillator ). VCTCXO is running at 26 MHz. Temperature effect is controlled with AFC ( automatic frequency control ) voltage. VCTCXO is locked into frequency of the base station. AFC is generated by baseband with a 11 bit conventional DAC in COBBA.
NSM–5 System Module PAMS Technical Documentation Receiver Receiver is a direct conversion, dualband linear receiver. Received RF– signal from the antenna is fed via RF–antenna switch to 1st RX dualband SAW filter and discrete LNAs (low noise amplifier), separate LNA branches for EGSM900 and DCS1800. Gain selection control of LNAs comes from HAGAR IC. Gain step is activated when RF–level in antenna is about –43 dBm.
PAMS Technical Documentation NSM–5 System Module Transmitter Transmitter chain consists of final frequency IQ–modulator, dualband power amplifier and a power control loop. I– and Q–signals are generated by baseband also in COBBA–ASIC. After post filtering (RC–network) they go into IQ–modulator in HAGAR. LO–signal for modulator is generated by VCO and is divided by 2 or by 4 depending on system mode, EGSM/DCS1800. After modulator the TX–signal is amplified and buffered.
NSM–5 System Module PAMS Technical Documentation DIR.COUPLER PA RF_OUT RF_IN K cp K PA R1 DETECTOR K K = –R1/R2 det ERROR AMPLIFIER R2 R C DOMINATING POLE TXC AGC strategy AGC–amplifier is used to maintain output level of the receiver in certain range. AGC has to be set before each received burst, this is called pre– monitoring. There is 50 dB accurate gain control (10 dB steps) and one larger step (~30 dB) in LNA. LNA AGC step size depends on channel with some amount.
NSM–5 System Module PAMS Technical Documentation comes in system clock has to be settled into +/– 0.1 ppm frequency accuracy. The VCTCXO–module requires also 5 ms to settle into final frequency. Amplitude rises into full swing in 1...2 ms, but frequency settling time is higher so this oscillator must be powered up early enough. DC–compensation DC compensation is made during DCN1 and DCN2 operations (controlled via serial bus).
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