User Guide

PAMS
Technical Documentation
NSB–1
System Module
Page 3 – 45
Original 06/98
Data Interface and Timing
PLUSSA is programmed via the serial bus SLE, SDAT and SCLK. The
data of SDAT is clocked by rising edge of SCLK. The data is fed MSB first
and address bits before data bits. The data for the Programmable dual
modulus counter is fed first and the Swallow counter last. SLE is kept low
while clocking the data.
During programming, the charge pump attached to programmed divider is
switched to high impedance state. Also all counters connected to the PLL
that is programmed, are kept on reset while the SLE is low.
Synthesizer Timing Control
SDATA/
SENA
SYNPWR
RXPWR
#bits 23 23 23 23 23
MODE VHF R VHF N/A UHF R UHF N/A
9.08us 9.08us
9.08 us
9.08 us
7.08 us
6.9 ms ( 1.5 x 4.6 ms ( frame )
100 us
2us min
SCLK
min.
Synthesizer Start–up Timing / Clocking