Block Diagram of System/RF Blocks Original 02/98 System Module UP8R NSE–1 3/A3–R1
Circuit Diagram of Baseband Original 02/98 System Module UP8R NSE–1 (Version 15.
Circuit Diagram of Power Supply (Version 15.
Circuit Diagram of SIM Connectors (Version 15.
Circuit Diagram of CPU Block (Version 15.
Circuit Diagram of Audio Original 02/98 System Module UP8R NSE–1 (Version 15 Edit 5) for layout version 15 3/A3–R6
Circuit Diagram of IR Module (Version 15.
Circuit Diagram of RF Block (Version Original 02/98 System Module UP8R NSE–1 15 Edit 8) for layout version 15 3/A3–R8
User Interface Connector (Version 15.
System Module UP8R Layout Diagram of UP8R – Top (Version 15) testpoint name condition dc–level J102 FBUS_RX power on pulsed DC (0V/2.8V) J103 MBUS power on pulsed DC (0V/2.8V) J107 LGND J110 VPP flash programming nominal 5V (5V flash) or 3.0V (3V flash) J111 WDDISX power on reset state 0V, normal state 2.
System Module UP8R Layout Diagram of UP8R – Bottom (Version 15) testpoint name condition dc–level J101 FBUS_TX active state pulsed DC (0V72.8V) J104 CCONTCSX (CCONT chip select) active state pulse active 0V, non–active 2.8V J108 CHRG_CTRL charger connected pulsed DC (0V/2.8V) J220 V5V active state nominal 5.0V (min 4.8V, max 5.2V) J223 CCONTINT (charger, RTC interrupt) interrupt pulse active 2.8V, non–active 0V J224 VCOBBA active state nominal 2.8V (min 2.7V, max 2.
