User Guide

NSE–1
System Module UP8S
Original 03/98
3/A3–S11
ac–leveldc–levelconditionnametestpoint ref
J516 VSYN_1 ( regulated supply for VCOs) 2.8 V min 2.7 / max 2.85 V
J518 VREF_2 ( ref. voltage for N500 ) 1.5 V +/– 1.5%
J520 AFC ( autom. freq. cntrl ) 0 – 2.3 V, typ. 1.15 V ( room temp. )
J522 VXO ( regulated supply for VCTCXO ) 2.8 V min 2.7 / max 2.85 V
J530&J532 71 MHz IF input to N620 –95 dBm @ X540
(ext. RF connector )
typ. ca. 1.2 V pulsed typ 100 – 140 uVpp balanced voltage at 71 MHz
J540 13 MHz output from N620 to Z620 –95 dBm @ X540
(ext. RF connector )
RXC at level of full
calibrated gain
typ. ca. 1.5 V pulsed typ. ca. 700 uVrms
J550 & J552 116 MHz TX IF to N500 typ. ca. 1.1 – 1.2 V pulsed typ. ca. 100 mVrms each
J562 RXC ( receive gain control voltage ) RX gain setting depended control range is 0.5 – 1.45 V, ,pulsed.
typ. 1.3–1.4 V for calibrated maximum gain
Layout Diagram of UP8S – Bottom (Version 9)
testpoint ref name condition dc–level ac–level
J101 FBUS_TX active state pulsed DC (0V72.8V)
J104 CCONTCSX (CCONT chip select) active state pulse active 0V, non–active 2.8V
J108 CHRG_CTRL charger connected pulsed DC (0V/2.8V)
J220 V5V active state nominal 5.0V (min 4.8V, max 5.2V)
J223 CCONTINT (charger, RTC interrupt) interrupt pulse active 2.8V, non–active 0V
J225 EXTSYSRESETX power on reset state 0V, normal state 2.8V
J226 VCXOPWR power on active state 2.8V, non–active 0V
J227 PURX (power on reset) power up/down reset state 0V, normal state 2.8V
J228 SLEEPCLK (32kHz clock) power on pulsed DC (0V/2.8V)
J235 ROM1SELX active state pulse active 0V, non–active 2.8V