User Guide

NSE–1
System Module UP8S
Original 03/98
3/A3–S10
Layout Diagram of UP8S – Top (Version 09)
testpoint ref name condition dc–level ac–level
J102 FBUS_RX power on pulsed DC (0V/2.8V)
J103 MBUS power on pulsed DC (0V/2.8V)
J107 LGND 0V
J110 VPP flash programming nominal 5V (5V flash) or 3.0V (3V flash)
J111 WDDISX power on reset state 0V, normal state 2.8V
J221 5V flash programming nominal 5.0V (5V flash) or 3.0V (3V flash)
J222 DSPXF power on pulse active 0V, non–active 2.8V
J224 VCOBBA active state nominal 2.8V (min 2.7V, max 2.85V)
J229 MAD selftest test mode set externally
J230 MAD selftest test mode set externally
J231 VSIM SIM power on nominal 2.8V (3V SIM card) or 5.0V (5V SIM card)
J232 VB (battery voltage in baseband) battery connected nominal 3.6V (min 3.0, max 4.2)
J233 RFCLK active state typ. 1.0Vpp (min 0.5Vpp, max 2.0Vpp)
J234 VSRM power on nominal 5.5V (min 5V, max 6V) CCONT switch mode regulator ripple voltage
J236 RAMSELX active state pulse active 0V, non–active 2.8V
J250 GND 0V
J252 COBBARSTX power on reset state 0V, normal state 2.8V
J253 COBBAWRX active state pulse active 0V, non–active 2.8V
J254 COBBARDX active state pulse active 0V, non–active 2.8V
J255 COBBACLK active state pulsed DC (0V/2.8V)
J502 Power control op.amp output voltage to N550 ( Vpd, pin ) power level depended pulsed DC
J506 RFC ( 13 MHz sinewave ) 0 V typ. 1.0 Vpp min 0.5/max 2.0 Vpp
J510 VRX ( regulated supply for RX ) 2.8 V min 2.7 / max 2.85 V, pulsed
J514 VTX ( regulated supply for TX ) 2.8 V min 2.7 / max 2.85 V, pulsed