User Guide

NPM-6/6X
System Module and User Interface CCS Technical Documentation
Page 28 Nokia Corporation. Issue 2 06/03
Power Up and Reset
Power up and reset is controlled by the UEM ASIC. NPM-6/6X baseband can be powered
up in following ways:
Press power button which means grounding the PWRONX pin on UEM
Connect the charger to the charger input
Supply battery voltage to the battery pin.
RTC Alarm, the RTC has been programmed to give an alarm
After receiving one of the above signals, the UEM counts a 20ms delay and then enters
its reset mode. The watchdog starts up, and if the battery voltage is greater than Vcoff+
a 200ms delay is started to allow references etc. to settle. After this delay elapses the
VFLASH1 regulator is enabled.
500us later VR3, VANA, VIO and VCORE are enabled. Finally the PURX line is held low for
20 ms. This reset, PURX, is fed to the baseband ASIC UPP, resets are generated for the
DSP and the MCU. During this reset phase the UEM forces the VCXO regulator on regard-
less of the status of the sleep control input signal to the UEM. The sleep signal from the
ASIC is used to reset the flash during power up and to put the flash in power down dur-
ing sleep. All baseband regulators are switched on at the UEM power on except for the
SIM regulator that is controlled by the MCU. The UEM internal watchdog is running dur-
ing the UEM reset state, with the longest watchdog time selected. If the watchdog
expires, the UEM returns to power off state. The UEM watchdog is internally acknowl-
edged at the rising edge of the PURX signal in order to always give the same watchdog
response time to the MCU.
A/D Channels
The UEM contains the following A/D converter channels that are used for several mea-
surement purpose. The general slow A/D converter is a 10 bit converter using the UEM
interface clock for the conversion. An interrupt will be given at the end of the measure-
ment.
The UEM’s 11-channel analog to digital converter is used to monitor charging functions,
battery functions, user interface and RF functions.
When the conversion is started the converter input is selected. Then the signal process-
ing block creates a data with MSB set to’1’ and others to’0’. In the D/A converter this
data controls the switches which connect the input reference voltage (VrefADC) to the
resistor network. The generated output voltage is compared with the input voltage under
measurement and if the latter is greater, MSB remains’1’ else it is set’0’. The following
step is to test the next bit and the next…until LSB is reached. The result is then stored to
ADCR register for UPP to read.
The monitored battery functions are battery voltage (VBATADC), battery type (BSI) and