User Guide

Table Of Contents

Mode Description

RESET RESET mode is a synonym for start-up sequence. RESET mode uses 32 kHz clock to count

the REST mode delay (typically 16ms).

SLEEP SLEEP mode is entered only from PWR_ON mode with the aid of SW when the system’s

activity is low.

FLASHING FLASHING mode is for SW downloading.

Clocking scheme

In BB5.0, two main clocks are provided to the system: 38.4MHz RF clock produced by VCTCXO in RF section

and 32.768kHz sleep clock produced by EM ASIC N2200 with an external crystal.

32 k Sleep Clock is always powered on after startup. Sleep clock is used by RAP for low-power operation.

SMPS Clk is 2.4 MHz clock line from RAP to EM ASIC N2300. In deep sleep mode, when VCTCXO is off, this signal

is set to '0'-state.

BT Clk is 38.4 MHz signal from Ahneus ASIC to BT module.

CLK600. The clock source is an internal RC oscillator in EM ASIC N2300 (during the power-up sequence) or

RAPIDO SMPS Clk.

Figure 17 Clocking scheme

USB, SIM, MicroSD

USB

USB (Universal Serial Bus) provides a wired connectivity between a PC and peripheral devices. It is a differential

serial bus.

USB 2.0 is supported with full speed (12 Mbps).

Hot swap is supported, which means that USB devices may be plugged in/out at any time.

This phone is provided with a specific connector for microUSB.

RM-429

System Module

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