User Guide

CC Technical Documentation System Module

NPM-10 (3595)

PLL Synthesizer, Functional Description

The frequency synthesis PLL, in conjunction with the VCO and 2/4 dividers, generates the

LO signal for both RX and TX paths, locked to the VCXO (which itself is locked to the base

station through the AFC).

Input to the PLL is the differential VCO and the 26 MHz reference oscillator signals. The

VCO signal is divided by a swallow counter consisting of a 64/65 dual modulus divider

and NDIV/ADIV dividers. The output of the NDIV/ADIV dividers is re-synchronized in the

phase detector with the output of the dual modulus divider to reduce phase noise.

The reference oscillator signal is divided by the RDIV divider to obtain a 400 kHz signal to

be used as reference in the Phase detector. The output of this divider is also

re-synchronized in the phase detector with the reference input to reduce phase noise.

The divided signals are compared in a phase detector, which controls the charge pump.

The output of the charge pump is connected to the external loop filter.

The average output current of the charge pump is a linear function of the phase

difference between the two input signals to the phase detector with a transfer constant

of approximately 1mA/2π. The transfer characteristic depends on which of the two

available phase detectors is selected.

One detector is the linear phase detector where the current in the current sources of the

charge pump is 1 mA independently of phase difference and a completely linear transfer

characteristic is achieved.

The other phase detector is the piecewise linear phase detector where the current is

reduced to 500 µA when sourcing and sinking current sources are active simultaneously.

This results in a constant slope transfer characteristic with two discontinuities.

The loop filter averages the pulses from the phase detector and generates a DC control

voltage to the VCO. The loop filter defines the step response of the PLL (settling time),

affects the stability of the loop, and performs reference sideband rejection.

The following figure shows a simplified block diagram of the synthesizer.

Figure 13: Simplified Synthesizer

VCO

CHARGE

PUMP

PHASE

DET.

f_out

Kvco

ref

f_out /

26 MHz frequency

FC-controlled