User Guide

CC Technical Documentation System Module

NPM-10 (3595)

The matrix detection requires that two lines are pulled low at the same time. The matrix

contains 15 keys. The six individual keys are detected by simple high-to-low transition

interrupt.

When the key has been detected, all the keypad registers inside the UPP are reset and it

is ready to receive a new interrupt.

RF Interface Block

The interface between the baseband and the RF can be divided into the following

categories:

• The digital interface from the UPP to the RF ASIC (Mjoelner). The serial digital

interface is used to control the operation of the different blocks in the RF ASICs.

• The analog interface between the UEM and the RF. The analog interface consists

of RX and TX converter signals. The power amplifier control signal TXC and the

AFC signal also are from the UEM.

Memory Module

The NPM-10 (3595) baseband memory module consists of 64-Mbit (8MB) external burst

type flash memory and 8-Mbit internal and 4-Mbit external SRAM.

Memory Interface

The memory interface consists of the MEMADDA [23:0] address/data bus, the

MEMCONT[9:0] memory control bus, and the GENIO[23], which also is used for memory

control.

The purpose of the memory interface is to reduce the amount of interconnections by

multiplexing the address and the data signals on the same bus. Because the required

flash address space is more than 16-bits, the MEMADDA[15:0] are multiplexed

address/data lines and MEMADDA[21:16] are only address lines, which in total allow for

4 M addresses (MEMADDA[21:0]). The multiplexed data/address lines require the memory

to store the address during the first cycle in the read/write access. Data access to the

flash is performed as a 16-bit access (MEMADDA[15:0]) in order to improve the data rate

on the bus.

The memory interface supports asynchronous read, burst mode synchronous read, and

simultaneous read-while-write/erase, all controlled by the UPP.

Memory Description

The 64-Mbit density flash with 16-bit data access operates in both asynchronous

random access and synchronous burst access (with crossing partition boundaries) and

has various data protection features. Upon power up or reset, the device defaults to

asynchronous read configuration. Synchronous burst read is indicated to the device by

writing to the flash configuration register and can be terminated by deactivating the

device.