User Guide

Nokia Customer Care Troubleshooting
Company Confidential RH-21
Issue 2 07/2004  2004 Nokia Corporation. Page 7
• Supply voltages stabilize to their UEM HW default values
• RFCLK grows to full swing
• The core is ready to run but waiting for the PURX release
• Reset releasing
• The UPP releases the SLEEPX up to the "non sleep" state to prevent the UEM
switching the regulators "OFF"
2 MCU starts running the Bootstrap Code
• written in stone/ UPP internal ROM
• the program checks if there is any reason for the FDL mode (Flash Down Load)
• If there is an executable code in FLASH and there is no reason for FDL, the MCU
starts running the MCU program from FLASH
3 MCU runs the FLASH MCU code
• the phone initialization, user interfaces, internal blocks, etc.
• Core regulator voltage setting for required DSP speed
• Initializes the DSP and concerning HW
• Releases DSP reset -> DSP starts running
Note: In the following figure, the RF_Clk frequency appears to be lower than 19.44MHz because of a
too low oscilloscope sampling frequency (2kS/s).
Figure 1: Power-up sequence