User Guide

NHM-8NX
System Module & UI PAMS Technical Documentation
Page 48 ãNokia Corporation Issue 1 05/02
locked instead of unlocked. The SW locking is similar to the Intel SW locking.
The AMD flash also has the same hardware lock as Intel. The blocks are locked if WP# is
set to low. If the WP# signal is driven high, the SW can control the locking of the blocks.
Finally, if the V
PP
pin is set to low all blocks are locked.
Memory Operation
Read
The flash allows asynchronous random access read and synchronous burst read.
CE# - low selects the device and puts it in asynchronous read mode. For all read modes,
WE# and RST# must be high. During asynchronous read mode, the read cycle is initiated
by first applying the address to MEMADDA[15:0]. AVD#-low opens the internal address
latches and the address is latched at the rising edge of AVD#. OE#-low activates the
output and places selected data on MEMADDA [15:0].
In synchronous mode, the address is latched either at the rising edge of AVD# or at the
rising edge of the CLK while AVD#-low, whichever occurs first. OE# low activates the
output and places selected data on MEMADDA [15:0]. The bus controller will activate the
WAIT signal as required to meet the memory random access time.
Synchronous burst mode improves the data transfer between the memory and the sys-
tem processor. Synchronous read allows for outputs of four, eight or continuous words,
as well as reads that cross partition boundaries. The CLK input increments an internal
burst address generator, uses the WAIT signal to synchronize the flash with the MCU in
the UPP and outputs data every clock cycle. Burst access may be initiated from any
address location except for the 8 parameter blocks.
The flash also supports other read modes: Read identifier, read query and read status reg-
ister which execute as single-synchronous or asynchronous read cycles. WAIT is inactive
during these reads.
Write
The write cycle requires WE# -low and OE# -high. All write operations are asynchronous.
The write cycle is initiated by first applying the address to the multiplexed address/data
bus and the address lines A21-A16. The address and data are latched on the rising edge
of the WE# signal.
Simultaneous Operation
Intel
The Intel device allows simultaneous read-while-write or read-while erase operations in
different partitions. The Program/Erase Suspend command halts in-progress erase or pro-
gram operations. The Suspend command allows data to be accessed from blocks other