User Guide

NHM-8NX
System Module & UI PAMS Technical Documentation
Page 46 ãNokia Corporation Issue 1 05/02
Since the internal capacitive load of digital circuits is lower than that of the intercon-
nect level at the PWB, the AMD device uses the PS signal to reduce the amount of
switching on the external bus and transfers the responsibility of signal state change to
the registers inside the flash or the UPP. The PS causes a minimum amount of transitions
on the MEMADD[23:0] bus by performing a bit-wise parity check of the data previously
on the bus with the data to be transmitted. If there are more equal bits than unequal
bits, the data is not inverted before being transmitted and PS remains low. If there are
more unequal bits than equal bits, the data is inverted inside the flash or UPP before
being transmitted on the bus and PS is driven high to indicate the inversion. PS-high at
the receiving end flags the inversion and the received data is inverted inside the flash or
the UPP before being stored or processed. The PS signal is a common signal for all the
devices connected to the MEMADDA[23:0] bus. Below is an example of how this signal
operates.
Figure 16: An XOR comparison of the data indicates more equal bits
Figure 17: An XOR comparison indicates more unequal bits
The Power Save function provides additional delay (10-15 ns) in random access, there-
fore it is only active in burst mode. Also, PS mode does not apply to the address, so the
address will always be presented in its true value. For burst access, it is possible to
remove the delay caused by the comparison logic by pipelining the power save function
and comparing the contents of the data in the burst with each other before putting it on
the bus. The PS function is disabled at initial power up and needs to be activated through
writing to the command register.