User Guide

NHM-8NX

System Module & UI PAMS Technical Documentation

Page 44 ãNokia Corporation Issue 1 05/02

while erasing or writing in Partition A. It can also suspend an erase in Partition A and

start writing to another block in Partition A. It resumes erase once the write is com-

pleted. Similarly, it is possible to read from Partition A and erase/write to partition B. It is

however, not possible to suspend an erase in partition B for writing to another block in

this partition.

Signal Descriptions

Both devices use similar signals with some minor deviations. The address/data signals are

connected to the MEMADDA[21:0] bus and the control signals (CE#, AVD#, etc.) are on

the MEMCONT[9:0] bus. Both devices have the same packaging and pin assignment.

Intel

The signal descriptions for the Intel device are listed in the following table:

Note: # indicates that the pin is active-low

Table 31: Intel signal description

Symbol Type Name and Function

A16-A21 I Address Inputs: for memory addresses

A/DQ0- A/

DQ15

I/O Address/Data Input/Outputs: Multiplexed address/data pins are address inputs while

ADV# is low. When ADV# goes high, address is internally latched and these signals

input/output data. Rising edge of WE# latches write data. Data is output when OE# is

low.

CE# I Chip Enable: CE#-low activates internal control logic, I/O buffers and decoders. CE#

high deselects the device, places it in stand-by state and places data and WAIT outputs

at high Z.

CLK I Clock: Synchronizes the device to the system bus frequency in synchronous-read con-

figuration and increments an internal burst address generator. During synchronous

read, addresses are latched on ADV# rising edge or clock CLK's rising while AVD# is

low, whichever occurs first.

ADV# I Address Valid: Indicates valid address presence on address input.

RST# I Reset: When low, it resets internal automation and provides data protection during

power transitions by inhibiting write operations. Exit from reset places the device in

asynchronous read mode.

OE# I Output Enable: When low, Activates the device's outputs through the data buffers dur-

ing a read cycle. When high, device outputs A/DQ15-0 and WAIT are disabled and

placed in high impedance state.

WE# I Write Enable: Controls writes to the device's command user interface and array.

Address and data is latched on the WE#'s rising edge.

WP# I Write Protect: Disables/Enables the lock down function when low. Locked down blocks

can not be unlocked through software alone.

WAIT O WAIT: Indicates data valid in synchronous read modes. It is high-Z until configuration

either high or low, with CE# high, it is high-Z.