User Guide

NHM-8NX
System Module & UI PAMS Technical Documentation
Page 42 ãNokia Corporation Issue 1 05/02
Cp1 represents the PWB capacitance on the Mjoelner side. Cp2 represents the PWB
capacitance on the UPP side together with the UPP input capacitance.
The Mjoelner's reference buffer is supplied from 2.8V and UPP's clock slicer is supplied
from 1.8V. Therefor a resistive voltage divider is used to limit the UPP input voltage
regardless of load capacitances.
• C426 is chosen so large that it resembles a short at 26MHz, but still so small that
it allows UPP to bias the input node (through Rbias) within a reasonable time.
Rbias is specified as maximum 100kohm, and with C426=1nF the time constant
for charging the input node is 100us. This is sufficiently fast, as the bias voltage
will be within 1% after 0.5ms. The reactance of 1nF is 6ohm at 26MHz.
• The ratio R420/R426 is chosen such that we get sufficient attenuation during
Mjoelner RESET. Disregarding C420, C426 and Cp2, we have Vupp=Vmjl*R426/
(R420+R426). It turns out that R420=R426 is a good candidate: If Mjoelner pro-
duces rail-to-rail swing (Vmjl=2.8Vpp) then there will be 1.4Vpp on the UPP side,
and the upper limit is 0.8*Vdd=1.44Vpp.
• R420 is chosen so small that it allows large load capacitances (Cp2) to be driven
through it, but still large enough that R420+R426 does not present too severe a
load. Assuming maximum Cp2=30pF, corresponding to a reactance of 204ohm,
and R420=R426 well above 204ohm, we will have Vupp=Vmjl*204ohm/R420.
Choosing R420=1kohm the UPP side gets 570mVpp, leaving good margin to the
lower limit of 300mVpp.
• C420 is chosen so small that any DC level jumps coming from Mjoelner are
quickly removed from the UPP side, but still large enough for C420 to have low
impedance compared to R420. Choosing C420=47pF, corresponding to a reac-
tance of 130ohm, the time constant for removal of DC jumps is
C420*(R420+R426)=94ns.
Memory Module
The NHM-8NX baseband memory module consists of 64-Mbit (8MB) external burst type
flash memory and 8Mbit internal SRAM, the SRAM is part of the UPP and will not be
covered here.
Memory Interface
The memory interface consists of the MEMADDA [23:0] address/data bus, the MEM-
CONT[9:0] memory control bus and the GENIO[23] which is used for memory control as
well.
The purpose of the memory interface is to reduce the amount of interconnections by
multiplexing the address and data signals on the same bus. Since the required flash
address space is more than 16-bits, the MEMADDA[15:0] are multiplexed address/data
lines and MEMADDA[21:16] are only address lines, which in total allow for 4M addresses
(MEMADDA[21:0]). The multiplexed data/address lines require the memory to store the