PAMS Technical Documentation NHM-8NX Series Transceivers System Module & UI Issue 1 05/02 ãNokia Corporation
NHM-8NX System Module & UI PAMS Technical Documentation Table of Contents Abbreviations ................................................................................................................. 4 Transceiver NHM-8NX - Baseband Module BF4A ...................................................... 5 Hardware characteristics in brief .................................................................................5 Technical Summary .......................................................................
PAMS Technical Documentation NHM-8NX System Module & UI RF frequency plan ................................................................................................... 68 DC characteristics ................................................................................................... 68 Functional descriptions ..............................................................................................71 RF block diagram .........................................................................
NHM-8NX System Module & UI PAMS Technical Documentation Abbreviations BSI Battery Size Indicator CTI Cover Type Indicator DCT4 Digital Core Technology, 4th Generation DSP Digital Signal Processor MCU MicroController Unit NO_SUPPLY UEM state where UEM has no supply what so ever PDM Pulse Density Modulation PWR_OFF UEM state where phone is off PWRONX Signal from power on key.
PAMS Technical Documentation NHM-8NX System Module & UI Transceiver NHM-8NX - Baseband Module BF4A This section specifies the baseband module for the NHM-8NX transceiver. The transceiver board is named BF4A, and all board references used refer to the board version BF4A_20. The baseband module includes the baseband engine chipset, the UI components and the acoustical parts for the transceiver.
NHM-8NX System Module & UI PAMS Technical Documentation Technical Summary The baseband module contains 2 main ASICs named the UEM and UPP. The baseband module furthermore contains an audio amplifier LM4890 for MIDI support and a 64Mbit Flash IC. The baseband is based on the DCT4 engine program.
NHM-8NX System Module & UI PAMS Technical Documentation The 32768 Hz clock is fed to the UPP as a sleep clock. The communication between the UEM and the UPP is done via the bi-directional serial buses CBUS and DBUS. The CBUS is controlled by the MCU and operates at a speed of 1 MHz. The DBUS is controlled by the DSP and operates at a speed of 13 MHz. Both processors are located in the UPP. The interface between the baseband and the RF section is mainly handled by the UEM ASIC.
NHM-8NX System Module & UI PAMS Technical Documentation Charger Input Voltage -0.3 ... 20V DC Characteristics Regulators and Supply Voltage Ranges Table 3: Battery voltage range Signal Min Nom Max Note VBAT 3.1V 3.6V 4.235V 3.1V SW cut off Table 4: BB regulators Signal Min Nom Max Note VANA 2.70V 2.78V 2.86V Imax = 80mA VFLASH1 2.70V 2.78V 2.86V Imax = 70mA ISleep = 1.5mA VFLASH2 2.70V 2.78V 2.86V Not used VSIM 1.745V 2.91V 1.8V 3.0V 1.855V 3.09V Imax = 25mA ISleep = 0.
NHM-8NX System Module & UI PAMS Technical Documentation VR7 2.70V 2.78V 2.86V Imax = 45mA Table 6: Current sources Signal Min Nom Max Note IPA1 and IPA2 0mA - 5mA Not used Internal Signals and Connections The tables below describe internal signals. The signal names can be found on the schematic for the bf4a PWB. Audio Table 7: Internal microphone Signal Min Nom Max Condition Note MIC1P (Differential input P) - - 100mVpp G=20dB 1kΩ to MIC1B (RC filtered by 220R/4.
NHM-8NX System Module & UI PAMS Technical Documentation XAUDIO[1] Filtered signal UEM, HF No direct connection between UEM and LM4890 LM4890 Output Swing 1.0 - Vpp with 60 dB signal to total distortion ratio VBAT Battery LM4890 (p. 6) Supply 3.1 4.2 V Lower limit is SW cut-off LCD Table 11: LCD connector interface Pin Signal NMP net 1 /RES XRES Parameter Min. Ty p. Max. Un it Reset - - 0.3 x VDDI V Logic Low, active 1000 - - ns For valid reset 0.
NHM-8NX System Module & UI PAMS Technical Documentation tPWL1 50 - - ns Serial clock low pulse width 6 VDD1 VDDI VDD digital power supply 1.72 1.8 1.88 V 7 VDD2in VDD Booster power supply 2.6 2.7 8 2.86 V VFLASH1 8 VLCD- VOUT Booster output - - 12 V Decoupled to GND on PCB with 1uF out Baseband – RF interface Table 12: BB – RF interface description Signal name From To RFICCNTRL (2:0) RFBUSEN1X RFBUSDA RFBUSCLK UPP Issue 1 05/02 Typ. Max.
NHM-8NX System Module & UI RXIINN RXQINP RXQINN TXIOUTP TXIOUTN Page 12 MJOE LNER MJOE LNER MJOE LNER UEM UEM PAMS Technical Documentation UEM UEM UEM MJOELNER MJOELNER Voltage swing 1.35 1.4 1.45 V DC level 1.3 1.35 1.4 V I/Q amplitude mismatch - - 0.2 DB I/Q phase mismatch -5 - 5 Deg. Data clock rate - - 13 MHz Voltage swing 1.35 1.4 1.45 V DC level 1.3 1.35 1.4 V I/Q amplitude mismatch - - 0.2 dB I/Q phase mismatch -5 - 5 Deg.
NHM-8NX System Module & UI PAMS Technical Documentation TXQOUTP TXQOUTN UEM UEM MJOELNER MJOELNER GENIO (28:0) 2.15 2.2 2.25 Vpp DC level 1.17 1.20 1.23 V Source impedance - - 200 W Data clock rate - - 13 MHz Differential voltage swing 2.15 2.2 2.25 Vpp DC level 1.17 1.20 1.23 V Source impedance - - 200 W Data clock rate - - 13 MHz UPP GENIO6 (RESETX_MJO EL) UPP MJOELNER Logic "1" 1.38 - 1.80 V Logic "0" 0 - 0.4 V MJOELNER Logic "1" 1.38 - 1.
NHM-8NX System Module & UI VR6 UEM VR7 UEM VREFRF01 VIO UEM PAMS Technical Documentation MJOELNER Output voltage 2.64 2.78 2.86 V Current 0.1 - 50 mA VCO Output voltage 2.64 2.78 2.86 V Current 0.1 - 45 mA Output voltage 1.33 4 1.35 1.36 6 V Current - - 100 µA Current - - 100 µA Output voltage 1.71 1.8 1.88 V Current 0.1 - 150 mA MJOELNER UEM MJOELNER Supply to: LNA's, Pregain Supply to: LO buffers, Local oscillators Used in MJOELNER (VBEXT) as 1.
NHM-8NX System Module & UI PAMS Technical Documentation VIO [1,8V] VDD18 VCORE [1,8V] VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDA VDD VDDI VDDDL SELADDR VDDSP1 VDDSP2 VDDSP3 VDDMCU VDDCORE1 VDDCORE2 VDDPDRAM1 VDDPDRAM2 VFLASH1 [2,78V] VDD28 BSI(pull up) PATEMP (pull up) VDD VSIM [1,8V / 3V] VSIM VR2 [2,78V] VDDDIG VDDTX TX section of MJOELNER sheet Current consumption during sleep Following section state the different regulators current consumption (theoretically excluding leakage in decoupling capaci
NHM-8NX System Module & UI PAMS Technical Documentation VCORE 1,8V PINS Current consumption in sleep (SLEEPX = low) UPP VDDSP1-3, VDDMCU, VDDCORE1-2 VDDPDRAM1-2 < 9 µA (Measured value < 120uA) Totally Specification: Max: 200uA Measured value < 120uA VFLASH1 2,78V PINS Current consumption in sleep (SLEEPX = low) UEM VDD28 < 5 µA BSI (pull up) < 30 µA PATEMP (pull up) < 25 µA LCD VDD <1100 µA Totally Specification: Max: 1500uA <1160 µA 1,8V / 3V PINS Current consumption in sleep (
NHM-8NX System Module & UI PAMS Technical Documentation 1 CHGND - 0 - Charger ground Table 16: External microphone Signal Min Nom Max Condition Note MIC2P (Differential input P) - - 100mVpp G=20dB 1kΩ to MIC1B MIC2N (Differential input N) - - 100mVpp G=20dB 1kΩ to GND MICB2 (Microphone Bias) 2.0 V 2.1 V 2.
NHM-8NX System Module & UI PAMS Technical Documentation Table 20: SIM Connector Pin Name Parameter Min Typ Max Unit Notes 1 CLK Frequency - 3.25 - MHz SIM clock Trise/Tfall - - 50 ns 1.8V SIM Card 1.62 0 ”1” ”0” VSIM 0.27 V 3V SIM Card 2.7 0 ”1” ”0” VSIM 0.45 V 1.8V SIM Card 1.6 1.8 2.0 V 3V SIM Card 2.8 3.0 3.2 V GND - 0 - V - - - 1.8V Voh 1.8V Vol 1.62 0 ”1” ”0” VSIM 0.27 3 Voh 3 Vol 2.7 0 ”1” ”0” VSIM 0.45 1.8V Vih 1.8V Vil 1.
PAMS Technical Documentation NHM-8NX System Module & UI Phone is exiting from NO_SUPPLY mode when sufficient battery voltage level is detected. Battery voltage can rise either by connecting a new battery with VBAT > VMSTR+ or by connecting charger and charging the battery above VMSTR+. Power_off In this state the phone is powered off, but supplied. VRTC regulator is active (enabled) having supply voltage from main battery.
NHM-8NX System Module & UI PAMS Technical Documentation VIO Enabled; Low Iq mode during sleep VCORE Enabled; Low Iq mode during sleep VSIM Controlled by register writing.
NHM-8NX System Module & UI PAMS Technical Documentation tionality can be found in next section. Charging NHM-8NX supports the NMP Janette Charger interface. Charging is controlled by the UEM ASIC, and external components are mounted for EMC, reverse polarity and transient protection of the input to the baseband module. The charger connection is through the system connector interface. Both 2- and 3-wire type chargers are supported.
NHM-8NX System Module & UI PAMS Technical Documentation Charge Control In active mode charging is controlled by UEM’s digital part. Charging voltage and current monitoring is used to limit charge into safe area. For that reason UEM has programmable charging cut-off limits VBATLim1,2L,2H (3.6V / 5.0V / 5.25V). Maximum charging current is limited to 1.2 A. Default for VBATLim is 3.6V (used for Initial charging of empty battery). VBATLim1,2L,2H are designed with hysteresis.
NHM-8NX System Module & UI PAMS Technical Documentation Table 22: Charger interface TVS characteristics: Breakdown voltage (VBR) 17.8Vmin (at IT 1.
NHM-8NX System Module & UI PAMS Technical Documentation Charging cut-off limits (programmable) VBATLim1+ VBATLim1VBATLim2L+ VBATLim2LVBATLim2H+ VBATLim2H- 3.54 3.32 4.85 4.65 5.10 4.90 3.65 3.50 5.0 4.85 5.25 5.10 3.76 3.66 5.15 5.05 5.40 5.30 V Charging switch resistance (includes bonding and leads) Temp =65°C (ambient) RSW - - 0.3 W PWM frequency (std charger) 0.5 1 1.5 Hz PWM duty cycle 0 - 100 % Switch output current slew rate SR 0.4 0.6 0.
PAMS Technical Documentation NHM-8NX System Module & UI the section Power Up and Reset. Pressing the power key causes the PWRONX pin on the UEM to be grounded. The UEM PWRONX signal is not part of the keypad matrix. The power key is only connected to the UEM. This means that when pressing the power key an interrupt is generated to the UPP that starts the MCU. The MCU then reads the UEM interrupt register and notice that it is a PWRONX interrupt.
NHM-8NX System Module & UI PAMS Technical Documentation A/D Channels The UEM contains the following A/D converter channels that are used for several measurement purposes. The general slow A/D converter is a 10 bit converter using the UEM interface clock for the conversion. An interrupt will be given at the end of the measurement.
NHM-8NX System Module & UI PAMS Technical Documentation Input voltage range (1) 0 - 2.7 V Input capacitance 4 5 6 pF . Table 25: Slow A/D converter input ranges Signal Min Typ Max Unit Note VBATADC 2.7 - 5.25 V Physical input on UEM is VBATREGS ICHAR VBATADC - VBATADC+0.316 V VCHARADC 0.1 - 1.35 V BSI 0 - 2.7 V BTEMP 0 - 2.7 V PATEMP 0 - 2.7 V Used for CTI VCXOTEMP 0 - 2.7 V Not used in NHM-8 HEADINT 0 - 2.7 V HOOKINT 0 - 2.7 V LS 0 - 2.
NHM-8NX System Module & UI PAMS Technical Documentation This A/D channel has a feature built into it that the charger voltage measurement can be specified to be performed when the charger switch is closed or open. This information is provided by the MCU when this channel is addressed. The charger measurement A/D channel can also be timed to the charger envelop detector in order to measure the standard charger peak voltage.
PAMS Technical Documentation NHM-8NX System Module & UI The keyboard light consists of 2 TBSF yellow/green LED's, which are placed under the keyboard and use the light guide to distribute the light LED driver circuit The LED drivers for LCD & Keyboard backlight are shared as shown below in Figure 4 Shared LED driver circuit for LCD and Keyboard backlight.The driver circuit is controlled by the UEM output pin [DLIGHT] and drive current is 15mA pr. LED.
NHM-8NX System Module & UI PAMS Technical Documentation The LCD is a black and white 96x65 full dot matrix display. The LCD has a standard DCT4 interface. The LCD interface between the LCD cell and the main PWB can be viewed in section LCD. The LCD cell is part of the complete LCD module, which includes metal frame, gasket, light guide, spring connector, transflector, dome sheet and earpiece. The figure below illustrates the complete overview of the LCD module.
NHM-8NX System Module & UI PAMS Technical Documentation and VIO for the driver chip. SIM Interface The UEM contains the SIM interface logic level shifting. The SIM supports 3V and 1.8V SIMs. SIM supply voltage is selected by a register in the UEM. It is only allowed to change the SIM supply voltage when the SIM IF is initialized. The SIM power up/down sequence is generated in the UEM. This means that the UEM generates the RST signal to the SIM. Also the SIMCardDet signal is connected to UEM.
NHM-8NX System Module & UI PAMS Technical Documentation The data communication between the card and the phone is asynchronous half duplex. The clock supplied to the card is 3.25 MHz. The data baudrate is SIM card clock frequency divided by 372 (by default), 64, 32 or 16. The protocol type, that is supported, is T=0 (asynchronous half duplex character transmission as defined in ISO 7816-3).
PAMS Technical Documentation NHM-8NX System Module & UI Figure 8: Speaker Interface UEM EARP 10 EARP EARN 10 EARN Earpiece Acoustic Design The earpiece acoustics is designed to be type approved by type 3.2, low leak artificial ear (Ear Simulator Type 4195, Low Leakage). Three different types of A-covers is used for NHM-8NX: Standard cover, gaming cover and DC-out cover. The gaming and DC-out covers is accessory covers. The std.
NHM-8NX System Module & UI PAMS Technical Documentation Below the earpiece is the PWB, where 4 holes will secure proper leakage to the volume between the PWB and the internal antenna. However since the PWB doesn't stretch all the way up to the top of the phone there will also be some natural leakage where the PWB is missing. Microphone electrical interface In NHM-8NX a differential bias circuit, driven directly from the MICB1 bias output with external RC-filters is chosen.
NHM-8NX System Module & UI PAMS Technical Documentation A new type of component is used for ringer melodies: a speaker. The speaker is a 13 mm device from PSS. It's inherited from the 13mm earpiece (also used by NHM-8) however with more height to provide opportunities for more displacement for the speaker diaphragm. The speaker have a protective shield directly in front of the diaphragm. The speaker substitutes the original buzzer.
NHM-8NX System Module & UI PAMS Technical Documentation NHM-8NX supports Li-Ion batteries.
NHM-8NX System Module & UI PAMS Technical Documentation Figure 12: Headset interface 2.7V Not all components are shown Hookint /MBUS EAD Headint Button Mic_bias MICB2 MIC2P MIC2N HF 1k0 2.1V MicGnd 1.8V 33N 33N 0.3V 0.8V 0.8V 3...25k HFCM 1k0 UEM Analog Audio Accessory Detection The accessory is detected by the HeadInt signal when the plug is inserted. Normally when no plug is present, the internal pull-down on the HF pin pulls down the HeadInt signal. HeadInt comparator value is 1.9V.
NHM-8NX System Module & UI 1 2 3 4 5 PAMS Technical Documentation Micbias is set to high impedance state HeadInt interrupt is detected EAD reading below 0.35V Micbias is set active 2.1V EAD reading 1.0V - 2.2V -> Headset connected Table 29: Headset identification Name Function Min Typ Max Uni t Description Headint Accessory detection 2.2 2.78 2.86 V Accessory connected Ead / hookint Micbias=High-Z 0.35 V Headset Micbias active 2.1V 1.009 1.07 1.163 V Headset button closed 1.
NHM-8NX System Module & UI PAMS Technical Documentation state. DC-OUT Interface A special type of electrically A-cover called "DC-Out cover" is supported by the phone via an electrical/mechanical interface connection. The kind of circuit, that has to be powered, can be anything from simple LED's to a "smarter" type of circuit. The implementation is designed to fulfil the below mentioned features: • • • No idle power consumption.
NHM-8NX System Module & UI PAMS Technical Documentation The power part consists of a current limited switch, and is controlled by a logic enable (on/off) via KLIGHT. On/off is synchronised with "VIBRA" signal SW wise, but can have independent SW control. Keyboard The keyboard used in NHM-8NX is partly matrix ("metal dome" type) and partly individually interrupts, this is needed for supporting multiplekeypresses.
NHM-8NX System Module & UI PAMS Technical Documentation The matrix detection requires that 2 lines are pulled low at the same time. The matrix contains 15 keys. The 6 individual keys are detected by simple high to low transition interrupt. When the key has been detected all the keypad-register inside the UPP is reset and it's ready receiving new interrupt.
NHM-8NX System Module & UI PAMS Technical Documentation Cp1 represents the PWB capacitance on the Mjoelner side. Cp2 represents the PWB capacitance on the UPP side together with the UPP input capacitance. The Mjoelner's reference buffer is supplied from 2.8V and UPP's clock slicer is supplied from 1.8V. Therefor a resistive voltage divider is used to limit the UPP input voltage regardless of load capacitances.
PAMS Technical Documentation NHM-8NX System Module & UI address during the first cycle in the read/write access. Data access to the flash is performed as a 16-bit access (MEMADDA[15:0]) in order to improve the data rate on the bus. The memory interface supports asynchronous read, burst mode synchronous read and simultaneous read-while-write/erase, all controlled by the UPP. Note: MEMADDA[23:22] is not used in this design.
NHM-8NX System Module & UI PAMS Technical Documentation while erasing or writing in Partition A. It can also suspend an erase in Partition A and start writing to another block in Partition A. It resumes erase once the write is completed. Similarly, it is possible to read from Partition A and erase/write to partition B. It is however, not possible to suspend an erase in partition B for writing to another block in this partition.
PAMS Technical Documentation NHM-8NX System Module & UI Vpp Pwr Erase and Program Power: A valid voltage on this pin (see above) allows block erase or data programming. For in-system (user mode) read, program and erase, Vpp=Vcc. Vpp=12 V for flashing during production. Extended use of 12V on this pin however, could damage the block cycling capability. Additionally Vpp serves as write protect if kept low.
NHM-8NX System Module & UI PAMS Technical Documentation Since the internal capacitive load of digital circuits is lower than that of the interconnect level at the PWB, the AMD device uses the PS signal to reduce the amount of switching on the external bus and transfers the responsibility of signal state change to the registers inside the flash or the UPP.
PAMS Technical Documentation NHM-8NX System Module & UI Block Locking Block locking is used to prevent accidental writing to some sectors in the flash. AMD and Intel will implement their block locking in the following ways. Currently, all block locking is done with software and the hardware locking with the WP# pin is not activated (in the hardware configuration software) and is therefore not used at all. Intel The locking scheme offers two levels of protection.
NHM-8NX System Module & UI PAMS Technical Documentation locked instead of unlocked. The SW locking is similar to the Intel SW locking. The AMD flash also has the same hardware lock as Intel. The blocks are locked if WP# is set to low. If the WP# signal is driven high, the SW can control the locking of the blocks. Finally, if the VPP pin is set to low all blocks are locked. Memory Operation Read The flash allows asynchronous random access read and synchronous burst read.
PAMS Technical Documentation NHM-8NX System Module & UI than the one being erased or programmed. An erase suspend allows system software to pause an erase so it can read or program data in another block, and a program suspend allows system software to pause programming so it can read (no erase possible) from other locations within that partition. AMD The device can perform simultaneous read-while-write or read-while-erase in different partitions. The AMD device only has the erase suspend feature.
NHM-8NX System Module & UI PAMS Technical Documentation Figure 18: Intel Asynchronous Read Asynchronous Read Intel AMD R1 tAVAV Read Cycle Time Min. 85ns R2 tAVQV Address to output delay Max. 85ns R3 tELQV CE# low to output delay Max. 85ns R4 tGLQV OE# low to output delay Max.
NHM-8NX System Module & UI PAMS Technical Documentation Figure 19: Intel Synchronous Four-Word Burst Read Synchronous Four-Word Burst Read Intel AMD R2 tAVQV Address to output delay Max. 85ns R304 tCHQV CLK to output delay Max. 14ns R305 tCHQX Output hold from CLK Min. 5ns R307 CLK to WAIT asserted Max. 14ns CE# low to WAIT active Max.
NHM-8NX System Module & UI PAMS Technical Documentation Figure 20: Intel Write Write Intel AMD W1 tPHWL Reset# High recovery to WE# low Min 150ns W2 tELWL CE# Setup to WE # low Min. 0ns W4 tDVWH Data setup to WE# High Min. 60ns W5 tAVWH Address setup to WE# High Min. 60ns W10 tVPWH Vpp setup to WE# high Min. 200ns W18 tVHWH ADV# setup to WE# high Min.
NHM-8NX System Module & UI PAMS Technical Documentation Figure 21: AMD Asynchronous Read Asynchronous Read tOE Output enable to output valid Max. 35ns tCE Access time from CE#-low Max. 90ns tACC Asynchronous Access time Max. 90ns Figure 22: AMD Synchronous Burst Read Synchronous Read tACC tAVDS Issue 1 05/02 Initial Access Time Max. 100ns AVD# setup time to CLK ãNokia Corporation Min.
NHM-8NX System Module & UI PAMS Technical Documentation tACS Address setup time to CLK Min. 5ns tOE Output enable to output valid Max. 35ns tCES CE# setup time to CLK Min. 5ns AMD Write Write tWC Write Cycle Time Min. 100ns tCS CE#-low setup time Min. 0ns tWP Write Pulse Width Min. 60ns Notes: 1.DIN is Data input to the device. 2.DQ7# is the output of the complement of the data written to the device. 3.DOUT is the output of the data written to the device.
PAMS Technical Documentation NHM-8NX System Module & UI nections between the UEM and the UPP. Baseband Power Up The baseband power is controlled by the programming jig in production, and the flash prommer (via the flashing battery) in reprogramming situations. Reprogramming uses the flashing battery to apply a supply voltage to the battery terminals and power up the baseband. The battery and supply voltage generated by the flash prommer interface equipment should not exceed 4.2 V.
NHM-8NX System Module & UI PAMS Technical Documentation flash prommer that it is ready to accept the secondary download code. All flash programming software is downloaded to the UPP internal MCU SRAM. The MCU also ends up in flash programming mode if the flash is empty, indicated by FFH in the first memory location in the flash. Flash Identifiers The flash has a manufacturer and device identifier for electrical identification.
PAMS Technical Documentation NHM-8NX System Module & UI This word contains information regarding the external SRAM if one is used for the baseband. The information specifies the size of the SRAM and the number of WAIT states to be used when accessing it. External SRAM is not supported by NHM-8NX. EMC Strategy The NHM-8NX phone complies with the given CE and SPR requirements concerning EMC and ESD.
NHM-8NX System Module & UI PAMS Technical Documentation The keyboard PWB layout consists of a grounded outer ring and either a "trefoil pattern" grid (matrix) or an inner pad. This construction makes the keys immune for ESD, as the keydome will have a low ohmic contact with the PWB ground. Power ON Key The power ON key interface on UEM (PWRONX) is protected via RC filtering and controlled PWB layout.
PAMS Technical Documentation NHM-8NX System Module & UI Charger lines Ground from charger is connected directly to common PWB ground for low impedance path to the battery. The positive charger line is ESD, EMC and short circuit protected by the circuit: F100, L100,C100 and V100. The routing is in shielded layer 5 to provide immunity to this line when in pulse charge mode and to obtain immunity from UEM IC.
NHM-8NX System Module & UI PAMS Technical Documentation Mechanical shielding NHM-8NX has metal shield over RF parts and BB parts to provide immunity for internal radiation and immunity for external fields. SIM card connector is placed below the battery to provide maximum immunity, to the SIM card, against RF fields from the antenna. Security The phone flash program and IMEI code are software protected, using an external security device that is connected between the phone and a PC.
NHM-8NX System Module & UI PAMS Technical Documentation FLASH Interface Flash programming in production is done through the test pads (X103) on the PWB. Flash programming is explained in section Flash Programming. Table 32: Flash interface signals Nom Max TX_D 2.7V 0V 3.0V RX_D 2.7V 0V 3.0V GND 0V SCK 2.7V 0V Signal Min Note 3.0V VPP 0V 12V Flash programming voltage BSI 0V 2.7V Battery size indication. Falling edge required for flash programming.
NHM-8NX System Module & UI MBUS PAMS Technical Documentation Vih 1.95V 2.7V 3.0V Vil 0V 0.2V 0.83V Voh 1.95V 2.78V 2.83V Vol 0V 0.2V 0.83V bidirectional Table 33 JTAG & Ostrich Interface JTAG & Ostrich are not supported on the bf4a board. DAI Digital Audio Interface (DAI) is used for audio testing. The audio samples are digitally transferred from DSP through FBUS at speed of 230.4 kbit/s. An 8 kHz synchronizing clock is needed for proper operation of DAI measurements.
NHM-8NX System Module & UI PAMS Technical Documentation • • • • • • • • LOCAL-state is for manufacturing, service and R&D -purposes Mobile terminal acts as a slave for the service PC Server can't start any action from event other than ISI messages UI inactive Permanent data, including UI data, reading/writing available with ISI messages through PERM server. SW entity must accept the factory set request Phone can't receive and create a call (CS in idle) Charging not allowed.
NHM-8NX System Module & UI PAMS Technical Documentation List of unused UEM pins Pin name Input/ output Note/description Required SW initialization. 3rd mic input not used. MUX should never be closed by SW Off MIC3P In MIC3N In KEYB1 In KEYB2 In LS In VCXOTEMP In PWMO Out PWM1C Out CHDISX In Disabling of UEM charger switch.
NHM-8NX System Module & UI PAMS Technical Documentation List of unused UPP pins R0 = pull-down, R1 = pull-up, CR0 = programmable pull-down, CR1 = programmable pull-up Name I/O Pull s Function (def. after reset) I/O Reset state JTClk I R0 JTAG Clock in R0 JTrst I R0 JTAG Reset.
NHM-8NX System Module & UI PAMS Technical Documentation GenIO25 I/O CR1 PUP: GenIO in/out In,CR1 out 1, CR1 GenIO27 I/O CR1 PUP: GenIO in/out In,CR1 out 1, CR1 GenIO28 I/O CR1 PUP: GenIO in/out out,1 out 1, CR1 Page 66 ãNokia Corporation Issue 1 05/02
PAMS Technical Documentation NHM-8NX System Module & UI Transceiver NHM-8NX - RF Module This section describes the RF module for the NHM-8NX transceiver. The RF module includes the RF chip, VCO, PA and surrounding components. NHM-8NX is a dualband E-GSM900/GSM1800 phone, with GPRS (Class 4). The RF engine is based on a RF chip called Mjoelner which contains all the RF functionality including LNA`s and reference oscillator. The engine is build for single-sided component mounting.
NHM-8NX System Module & UI PAMS Technical Documentation Main Technical specifications Temperature conditions Environmental condition Ambient temperature Remarks Normal operation - 10º … +55ºC Specification fulfilled Reduced performance - 30º.. – 10ºC and + 55ºC .. +85ºC Storage temperature range < - 30ºC or > +85ºC No storage or operation. An attempt tp operate may damage the phone permanently Nominal and maximum ratings Parameter Rating Battery voltage nominal 3.
NHM-8NX System Module & UI PAMS Technical Documentation All regulators can be controlled individually with 2.78V logic directly or through control register. Use of the regulators can be seen in the power distribution diagram. VrefRF01 is used as the reference voltages for the RX ADC`s reference in Mjoelner. The regulators are connected to Mjoelner, either directly or through output loading networks.
NHM-8NX System Module & UI PAMS Technical Documentation Idle 1.2 mA RX 84 mA, peak TX, without PA 141 mA, peak Including TX buffer & RX/TX switch TX, power level 5, EGSM 1700 mA, peak Efficiency 48% (at max power – 1 dB) TX, power level 0, GSM1800 1220 mA, peak Efficiency 40% (at max power – 1 dB) Figure 25: Power distribution diagram Internal Mjoelner VR2 2.78 V +/- 3% @ 100 mA TX modulator Power Loop Amp Modulator loading network VR3 2.
NHM-8NX System Module & UI PAMS Technical Documentation Functional descriptions RF block diagram Block diagrams of direct conversion receiver and transmitter RF section has described in the following figure. The architecture is based on Mjoelner, the RF ASIC, which contains most of the functionality of the RF Engine. The ASIC contains RX and TX functions, VCXO (crystal is placed external to the ASIC), se the block diagram.
NHM-8NX System Module & UI PAMS Technical Documentation the range of 3420 to 3840 MHz, and the use of a VCO module enables the possibility of different vendors for the same component. PLL Synthesizer, Functional Description The frequency synthesis PLL in conjunction with the VCO and 2/4 dividers generates the LO signal for both RX and TX paths, locked to the VCXO which again is locked to the base station through the AFC. Input to the PLL is the differential VCO and the 26 MHz reference oscillator signals.
NHM-8NX System Module & UI PAMS Technical Documentation Figure 27: Simplified Synthesizer 26 MHz frequency R AFC-controlled LP fref f_out /M PHASE CHARGE DET. PUMP f_out VCO Kd Kvco M Receiver The Receiver is a dual band, direct conversion, linear receiver. The received RF signal is routed from the antenna to the RX/TX switch. The RX/TX switch performs both the switching between receive – transmit routing of the antenna signals as well as the selection of the band to be used.
NHM-8NX System Module & UI PAMS Technical Documentation The receiver selectivity for out-of-band signals is defined by the RF front-end SAW filter. The receiver ability to withstand large out-of-band signals is defined by the RF SAW filter and the large signal behavior of the LNA – pregain and mixer. The inband selectivity is define by the 91 kHz channel filters in Mjoelner, and the in-band large signal behavior is a combination of the RF front-end and the BB amplifier large signal behavior.
NHM-8NX System Module & UI PAMS Technical Documentation The DC compensation is carried out to compensate for the un-avoidable dc offset in the BB amplifiers, the self mixing results from the LO and the mixing of blocking signals. The DC compensation is carried out by two individual circuits. One circuit (DCN1) compensates for the off-set while the other circuit (DCN2) centers the signal center level to match the succeeding A/D converter. The principle of the DC-compensation is shown in figure 8.
NHM-8NX System Module & UI PAMS Technical Documentation The outputs from the individual PA chains is feed to individual couplers, that means one for GSM and one for PCN, before entering the RX/TX switch. The harmonics from the PA is filtered by filters located in the RX/TX switch.
NHM-8NX System Module & UI PAMS Technical Documentation included in Mjoelner) is controlled via the serial data contained in three control lines, a chip select, a clock line and a serial data line. RF characteristics Channel numbers and frequencies Table 36: Channel no. relative frequencies System Channel number TX frequency RX frequency Unit E-GSM 0 <= n <= 124 975 <= n <= 1023 F = 890 + 0.2 * n F = 890 + 0.2 * (n –1024) F = 935 + 0.2 * n F = 935 + 0.
NHM-8NX System Module & UI PAMS Technical Documentation Output power tolerance (power level 5) +/- 2.0 +/- 2.5 dB, normal cond. dB, extreme cond. Output power tolerance (power levels 6...15) +/- 3.0 +/- 4.0 dB, normal cond. dB, extreme cond. Output power tolerance (power levels 16...19) +/- 5.0 +/- 6.0 dB, normal cond. dB, extreme cond. 3.5 dB Output power control step size 0.5 2.
NHM-8NX System Module & UI PAMS Technical Documentation Table 42: Output RF spectrum due to modulation, requirements, GSM1800 Output modulation spectrum - GSM1800 Power level 100 kHz 200 kHz 250 kHz 400 kHz 600 to 1800 kHz Measurements BW: 30 kHz 30 dBm Unit Measurements BW: 100 kHz -73 dBc 28 dBm -63 -71 dBc 26 dBm -61 -69 dBc < 24 dBm -59 -67 dBc -51 -51 dBm -36 -30 > 6000 kHz -65 Minimum abs. Level +0.
NHM-8NX System Module & UI PAMS Technical Documentation Spurious emission (when allocated a channel) Table 44: Spurious emissions requirements, when allocated a channel, E-GSM / GSM1800 Spurious emission ( when allocated a channel ) Frequency range Min Typ Max E-GSM Unit / Notes GSM1800 9 kHz ... 925 MHz -36 dBm 925 MHz ... 935 MHz -67 dBm (*) 935 MHz ... 960 MHz -79 dBm (*) 960 MHz ... 1000 MHz -36 dBm 1000 MHz ... 1710 MHz -30 -30 dBm 1710 MHz ... 1785 MHz -36 dBm 1785 MHz ...
NHM-8NX System Module & UI PAMS Technical Documentation Frequency error - E-GSM Table 47: Frequency error, E-GSM Frequency error - E-GSM Propagation condition Min Typ Max Unit Static channel +/- 0.1 ppm TU3 +/- 230 Hz TU50 +/- 160 Hz HT100 +/- 180 Hz RA250 +/- 300 Hz Frequency error - GSM1800 Table 48: Frequency error, GSM1800 Frequency error - GSM1800 Propagation condition Min Typ Max Unit Static channel +/- 0.1 ppm TU1.
NHM-8NX System Module & UI PAMS Technical Documentation Sensitivity (2) Min. –102 dBm Min. –102 dBm (1) Sensitivity required for production 2% BER Min. –105.5 dBm (3) Min. –105.5 dBm (3) Total typical receiver voltage gain (from antenna to RX ADC) 94 dB Receiver output level (RF level –95 dBm) 125 – 250 mVpp, Typical AGC dynamic range 92 dB Accurate AGC control range 72 dB Typical AGC step in LNA ~30 dB Usable input dynamic range -102... –10 dBm RSSI dynamic range -110...
NHM-8NX System Module & UI PAMS Technical Documentation 1.6 MHz <= f – fo < 3 MHz -33 3 MHz <= f – fo -26 100 kHz < = f < 1705 MHz 0 1705 MHz < = f < 1785 MHz -12 1920 MHz < = f < 1980 MHz -12 1980 MHz < = f < 12.
NHM-8NX System Module & UI PAMS Technical Documentation Spurious response rejection 54 (*) dB, (-43 – (-100+3)) TSpurious emission requirements - E-GSM and GSM1800 Table 55: Spurious emissions RX requirements Spurious emission requirements - E-GSM and GSM1800 Frequency range Min Typ Max Unit / Notes 9 kHz ... 925 MHz -57 dBm 925 MHz ... 935 MHz -67 dBm (*) 935 MHz ... 960 MHz -79 dBm (*) 960 MHz ... 1000 MHz -57 dBm 1000 MHz ... 1805 MHz -47 dBm 1805 MHz ...
