User Guide

Nokia Customer Care System Module
RH-37
Issue 1 07/04 Nokia Corporation Page 53
grated in the RF ASIC (Helgo) except for the VCTCXO, VCO, and the loop filter.
The VCTCXO (Voltage Controlled Temperature Compensated Crystal Oscillator) generates
the clock frequency of 26 MHz. This frequency is buffered in the RF ASIC and fed to the
UPP. Additionally, it is used as the reference frequency for the RF PLL. The frequency of
the VCTCXO is locked into the frequency of the base station with the help of an AFC volt-
age which is generated in the UEM by an 11 bit D/A converter.
The PLL (phase locked loop) locks the VCO frequency into a stable frequency source,
given by the VCTCXO. The PLL is located in the RF ASIC and is controlled through the
RFBus.
The loop filter generates a DC control voltage for the VCO from the charge pump pulses
of the phase detector. The loop filter determines the step response of the PLL (settling
time) and contributes to the stability of the loop.
Signal paths
Receiver signal paths
From the antenna-pad, the RF signal is fed directly to the antenna switch module.
Depending on the control signals VC1, VC2, VC3, the antenna port is connected to one of
the Rx ports RX1, RX2, RX3. From these ports the signal is passed on to the band filters:
• GSM 900: RX1‡GSM900 SAW filter
• GSM1800: RX2‡ GSM1800 SAW filter
• GSM1900: RX3‡ GSM1900 SAW filter
The antenna switch has the following typical insertion losses in the Rx mode from its
LB LP
FILTER
VCO Module
VR7
2 dB
Att
Balun
900 Rx
SAW
1800 Rx
SAW
BUILT-IN DC COMP.
AND AGC FUNCTION
LOW-PASS FILTERS
INTEGRATED
VBB
1900 Rx
SAW
Balun
VBB
GPIO
10mA
2.7V
VLO
by 2/4
Divide
Serial
Bi-directional
Interface
ESD
HB BP
LC
900 Tx
LC
LC
1900 Tx
LC
SCLK
SLE
SDATA
RESET
CTRL inputs
VDIG
VRF_RXVLNA
Rx part of RF ASIC
VRF_TX,VBB,VLO,VTX
RXIP
RXQP
VF_RX
VCP
VR1
VR2
VRF_TX
LNAB_P
LNA_P
VDIG
VR3
VF_RX
VPAB_VLNA
VRF_RX
VR4
VLO
VPRE
VR5
VBB
VR6
Antenna
Switch
Module
Rx part of RF ASIC