User Guide

PAMS
Technical Documentation
NSE–8/9
System Module
Page 2– 42
Issue 1 07/99
Cobba_GJP uses the 13 MHz clock,COBBACLK, coming from MAD2PR1
as a system clock. The 520KHz PCM codec master clock,PCMDClk, and
the 8 KHz PCM codec frame synchronization clock,PCMSClk, are the two
PCM codec related clocks going from COBBA_GJP to MAD2PR1 . The
master clock is used to clock the transfer of the PCM samples between
COBBA PCM codec and MAD2PR1 DSP. The frame synchronization clock
frequency is used to indicate the sample rate of the PCM samples.
A 3.25 MHz synthesizer clock, SynthClk, is used to load the synthesizers.
The clock is generated in MAD2PR1 and it goes to SUMMA in RF.
MAD2PR1 provides the SIM clock, 3.25 MHz, to the SIM card via CCONT
SIM interface.
The MAD2PR1 general purpose serial output, GenSIO_0, is a 1.083 MHz
clock which is used in the communication between MAD2PR1 – CCONT
and MAD2PR1 – LCD driver.
The LCD driver IC is equipped with an internal free running clock oscillator
of typically 16.3 KHz used for internal logical operation and divided into
the display frame frequency of 80 Hz.
Resets and Watchdogs
This section describes the resets and the watchdogs of the system. They
are described together because they are linked together, i.e. expired of a
certain watchdog causes a certain reset to happen.
MAD2PR1
COBBA_GJP
LCD DRIVER
CCONT

SYSTEM
RESET


SIM RESET
LCD DRIVER RESET
PURXCCONT
WATCHDOG
SOFT
WATCHDOG
COBBA
RESET
Flash Rom
RAM
LCDRSTX
Figure 9. Reset Scheme