User Guide

PAMS
Technical Documentation
NSE–8/9
System Module
Page 2– 41
Issue 1 07/99
Clocking Concept
This section describes the main clocks in the system.
MAD2PR1
VCXO
COBBA_GJP
LCD DRIVER
CCONT
13 MHz
SINE
WAVE
13 MHz
520KHz PCM
8 kHz PCM SYNC
3.25 MHz SYNTE CLK
SIM CLK
GENSIO_0
32 kHz SLEEP
CLOCK



Summa
AFC

 

1.083MHz
3.25 MHz
DSP
PLL
13 MHz
52 MHz
osc
16.3KHz
Figure 8. Clocking Scheme
The system clock in the HD947 phone is 13 MHz. It is generated in the
RF VCTCXO circuit. The clock frequency is controlled by AFC which is in
COBBA_GJP. The 13 MHz sine wave signal goes to MAD2PR1 RFC block
which generates a square wave signal from the sine wave signal.
MAD2PR1 provides the clocks to its internal system components from the
13 MHz system clock. The MCU receives 13 MHz clock. For the DSP the
MAD2PR1 system logic provides an 13 MHz clock which is up converted
by the DSP PLL 52 MHz. MAD2PR1 generates also the clocks to its own
system logic blocks.
The real time clock logic consists of RTC logic in CCONT, and the 32
kHz crystal.
In normal situation the real time clock takes the power from the switcher
output. When the cutoff voltage is reached the switcher continues to
operate at least 24h, providing supply for the RTC.
In case the main battery is removed the RTC is powered by the output
capacitors on the switcher until they are drained and the RTC loses it’s
timing. The time must be set again upon power on.
CCONT generates a 32 kHz sleep clock signal which is used as a time
base during the sleep state. The 32 kHz clock signal goes to MAD2PR1
which has the sleep state counter. Sleep clock output to MAD2PR1 is
active always when the phone is powered on.