User Guide

PAMS
Technical Documentation
NSE–8/9
System Module
Page 2– 23
Issue 1 07/99
Table 14. CPU connections (continued)
RemarkTypeName
of signal
PCM(3:0) bus communication line beteween MAD2PR1 and COBBA_GJP for receive
and transmit data for the audio transmission.
COBBACLK output 13MHz clock for the synchronization COBBA
COBBA
RESET
output Reset signal from MAD2PR1 to Cobba_GJP
COL(3:0) output Column addresses for the keyboard scan
ROW(4:0) input Row addresses from the keyboard scan and power–on key.
BUZZER output PWM output from MAD2PR1 to the Buzzer driver in UISWITCH
LCDCD output Control line to the LCD driver
LCDEN output Chip select to the LCD driver
LCDRSTX output Reset of the LCD driver
VCON_1 output Least significant bit in the 2–bit DAC control of the DC/DC–converter out-
put voltage.
VCON_2 output Most significant bit in the 2–bit DAC control of the DC/DC–converter out-
put voltage.
LOW_BATT Input Battery removal alert to MAD2PR1
BTEMP Input connection to provide access to BTEMP signal in production and service
SDATA output Serial data for the synthesizer inside SUMMA in the RF
SCLK Output 13/4 MHz clock for the serial communication with the synthesizer inside
SUMMA in RF
SENA1 output Chip select for the serial communication with SUMMA in RF
FRACTRL output Controls signal for the gain in the LNA in the RF
TXP output Logical control signal to indicate the power on of the TX circuitry
RFC Input 13MHz system clock from the RF
BAND_SEL output Logical control of the band selection in the front end GSM 900 or DCS
1800
Table 15. POWER connections
Name
of signal
Type Remark
V_CHARGE_IN input charger voltage input
CHARGE_GND input charger current return
CHARG_CTRL output Charger voltage control signal
PSCC_PWM input Logical signal from MAD controlling the charger switch inside PSCC,
High switch open, Low switch closed
CHARG_OFF input Logical signal from MAD enabling / disabling charging through PSCC,
High disables both start– and PWM–charging.