PAMS Technical Documentation NSE–8/9 Series Transceivers Chapter 2 System Module Issue 1 07/99
NSE–8/9 System Module PAMS Technical Documentation Contents Page No Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAMS Technical Documentation NSE–8/9 System Module RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NSE–8/9 System Module PAMS Technical Documentation Table of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. SIM connector, X100 and Battery terminals, . . . . . . . . . . . . . . Display Connector pin location . . . . . . . . . . . . . . . . . . . . . . . . . .
PAMS NSE–8/9 Technical Documentation System Module Technical Information HD947 is a DCT3.5 based product, i.e. a dual band GSM 900 & DCS1800, single board concept using the serial version of the MAD2PR1– and COBBA_GJP chip set. HD947 is based on HD945 (PICA) HW with significant modifications in the Baseband as listed below: – HD947 uses a two cell semi fixed NiMH battery–pack only, giving 2.4V nominal supply voltage. Thus the usual NMP battery interface is modified.
PAMS NSE–8/9 System Module Technical Documentation Operating Modes 1. Acting Dead: If the phone is off and the switcher is operating with the lowest output voltage and a charger is connected, the Baseband is powered on but enters a state called ”acting dead”. To the user the phone acts as if it was switched off. A battery charging alert is given and/or a battery charging indication on the display is shown to acknowledge the user that the battery is being charged. 2.
PAMS NSE–8/9 System Module Technical Documentation Maximum ratings Table 1. Maximum ratings Parameter Rating Condition Battery voltage, idle mode –0.3 ... 3.6 V Max voltage at which the battery can be charged by the phone Charger input voltage –5.0 ... 18V Max voltage which activates the PSCC input over–voltage protection Temperature range DC Characteristics Table 2. Battery & DC/DC converter Voltages Line Symbol Signal Name Min Typ Max Unit Battery Supply voltage Vb 1.9 2.4 3.
PAMS NSE–8/9 System Module Technical Documentation Table 3. DC/DC converter output voltages when in TX–mode Line Symbol Condition ** Min Typ Max (continued) Unit Vcon1 Vcon2 Vdc_out 900MHz 3.2 3.4 3.6 V *** current in TX burst @Vdc_out min * n/a *) n/a *) 1360 mArms Current between TX burst n/a *) n/a *) 150 mArms 3.7 3.9 4.1 V *** current in TX burst @Vdc_out min * n/a *) n/a *) 2650 mArms Current between TX burst n/a *) n/a *) 150 mArms 3.8 4.0 4.
PAMS NSE–8/9 System Module Technical Documentation Table 4. DC/DC converter output voltages when non Tx–mode Line Symbol Vcon1 Vcon2 Condition Minimum Nominal Vdc_out Low Vdc_out Maximum Unit Comment Low 3.1 3.3 3.5 V Off mode Low Low 3.1 3.3 3.5 V Sleep mode Vdc_out Low Low 3.1 3.3 3.5 V Active mode non TX Vdc_out Low Low 3.1 3.3 3.5 V Acting dead mode Vdc_out high high 3.8 4.0 4.2 V for buzzer & vibra operation Table 5.
PAMS NSE–8/9 System Module Technical Documentation External Signals and Connections This section lists and specifies all the electrical connections from the Baseband part of the transceiver, i.e. either to the outside world (Bottom– , SIM card– and battery connector) , or to items in the mechanical assembly that has electrical interface (LCD, Vibra, speaker and microphone). Table 6.
PAMS NSE–8/9 System Module Technical Documentation Table 7. SIM Connector , X100 Pin Name Parameter Min 1 GND GND 0 2, 6 VSIM 5V SIM Card 4.8 3V SIM Card 5V Vin/Vout 3 DATA Max Unit Notes 0 V Reference ground for the SIM interface signals 5.0 5.2 V Supply voltage 2.8 3.0 3.2 4.0 ”1” VSIM V SIM data 0 ”0” 0.4 2.8 ”1” VSIM 0 ”0” 0.4 5V SIM Card 4.0 ”1” VSIM V 3V SIM Card 2.8 ”1” VSIM V 5V SIM Card 0 ”0” 0.4 V 3V SIM Card 0 ”0” 0.
PAMS NSE–8/9 System Module Technical Documentation Display connector Pad 8 Figure 2. Pad 1 Display Connector pin location Table 9. Display connector, X400 P i n Signal Symbol 1 VBB Parameter Supply voltage 2 GenSIO_0 fEXT Serial clock input Min. Typ. Max. Unit Notes 2.7 2.8 3.3 V range that LCD supports 300 uA +25 °C, VL= 2.8 V, LCDCSX is disabled with Special Test Pattern ”12345” 4.00 MHz 0 tscyc 250 ns tshw 100 ns tslw 100 ns ViH 0.
PAMS NSE–8/9 System Module Technical Documentation Table 9. Display connector, X400 P i n Signal Symbol Parameter Max. Unit 0.3xVbb V Logic low 10 ns Rise / fall time 100 ns Setup time tsah 100 ns Hold time ViL 0 0.3xVbb V Logic low, Control data ViH 0.7xVbb Vbb V Logic high, Display data 10 ns Rise / fall time ViL Min. (continued) Typ. 0 tr / tf 4 LCDCD tsas Control/display data flag input tr / tf 5 LCDEN tcss Chip select input 60 ns tcsh 100 ns ViH 0.
PAMS NSE–8/9 System Module Technical Documentation LCDEN GenSIO_1 GenSIO_0 D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 D7 9 D6 10 LCDCD Serial interface timing tcss tcsh LCDEN tsas tsah LCDCD tscyc tslw GenSIO_0 tshw tf tr tsds GenSIO_1 tsdh Data Detailed Serial Interface timing trw LCDRSTX tinit Driver internal state In reset Ready Driver Reset timing Page 2– 14 Issue 1 07/99
PAMS NSE–8/9 System Module Technical Documentation Bottom Connector Microphone well 2, IMICP D–cover to PCB gronund 3, IMICN D–cover to PCB gronund 1 Charge_GND Mic sound port 4,5,6,7,8 Audio Jack 13, V_charge_in Pad 10,11,12 Charger Jack 9, Charge_Ctrl, pad Figure 3. Bottom Connector, X503, pin locations (top View) Charge_GND 1 D–cover to PCB GND Mic sound port D–cover to PCB GND 2 15 1 Charger Jack 10,11,12 9 4,5,6,7,8 3 15 4 Figure 4.
PAMS NSE–8/9 System Module Technical Documentation Table 10. Signals of the bottom connector X503 Pin Name Parameter Min 1, 10 Charge _GND Charger return –0.3 2 IMICP IMICP 3 IMICN IMICN 4 INT Headint low 5 XEarP *) Typ Max Unit 0 V 0.55 4.1 mV 0.55 4.1 mV 0.57 0.65 0.72 V No plug inserted in audio jack Headint high Vbbmin Vbb Vbbmax V Plug inserted in audio Jack positive line for external audio output 113 150 188 Ω Output AC impedance (ref.
PAMS NSE–8/9 System Module Technical Documentation Table 10. Signals of the bottom connector X503 (continued) Pin Name Parameter 6 XMicN *) Negative line for external audio input to phone Min Typ Max Unit Notes 0.025 Vpp Maximum input signal level (ref. XMicP) with Cobba gain 18dB, 300< f <3400 Hz 40 HDC–5 mode 775 895 dB/dec Input attenuation, f<300 Hz (ref. XMicP) 995 mV Hook active DC level ref. gnd 95 380 mV Hook in–active DC level ref. gnd –100 –400 µA Bias current (ref.
PAMS NSE–8/9 System Module Technical Documentation Table 10. Signals of the bottom connector X503 (continued) Pin Name Parameter 8 XMicP *) Positive line for external audio input to phone Min Typ Max Unit Notes 0.025 Vpp Maximum input signal level (ref. XMicN) with Cobba gain 18dB, 300< f <3400 Hz 40 HDC–5 mode dB/dec Attenuation of input inside phone, f<300 Hz (ref. XMicN) 1450 2090 mV Headset identification DC level ref. gnd @ AUXout = 2.
PAMS NSE–8/9 System Module Technical Documentation Table 10. Signals of the bottom connector X503 (continued) Pin Name Parameter Min Typ Max Unit 11. 13 V_char ge_IN Charger voltage input, 7.25 7.6 7.95 Vrms 11.1 16.9 Vp Unloaded Peak voltage ACP–7 type 320 370 420 mA Supply current 1.1 Apeak Supply current Unloaded ACP–8 Charger ACP–8 type ACP–9 type 5.7 6.0 6.3 Vrms 500 620 750 mA 7.1 8.4 9.3 Vrms 6.0 7.1 8.
PAMS NSE–8/9 System Module Technical Documentation Table 11. Internal Earpiece connection, B201 Pad Name Min Typ Max Unit Remark 1 EARN 0 14 220 mVac Connected to COBBA_GJP EARN output. Typical level corresponds to –16 dBmO network level with volume control giving nominal RLR (=+2dB) 8 db below max. Max level is 0dBmO with max volume (codec gain –11 db) 2 EARP 0 14 220 mVac Connected to COBBA_GJP EARP output.
PAMS NSE–8/9 System Module Technical Documentation Table 12. Vibra motor connection, E103 & E104 Pad Name Min Typ Max Unit E103 to E104 Rated voltage 1.3 V E103 to E104 Rated current 116 mA rms E103 to E104 Operating voltage 1.2 E103 to E104 Start voltage 1.1 E103 to E104 Start current E103 to E104 internal resistance 1.9 Comment V rms V rms 135 mA rms 10.
PAMS NSE–8/9 System Module Technical Documentation Table 13.
PAMS NSE–8/9 System Module Technical Documentation Table 14. CPU connections Name of signal PCM(3:0) Type bus (continued) Remark communication line beteween MAD2PR1 and COBBA_GJP for receive and transmit data for the audio transmission.
PAMS NSE–8/9 System Module Technical Documentation Table 15.
PAMS NSE–8/9 System Module Technical Documentation Table 16. UI connections Name of signal Type (continued) Remark LCDEN input Chip select to the LCD driver LCDRSTX input Reset of the LCD driver VIBRA input PWM output from MAD2PR1 to the vibra driver in the UISWITCH KEY_LIGHT input Logical signal controlling the keyboard backlight driver in the UISwitch. LCD_LIGHT input Logical signal controlling the LCD backlight driver in the UISwitch.
PAMS NSE–8/9 System Module Technical Documentation Table 18. AC and DC Characteristics of signals between Baseband and RF Signal name From To Parameter Minimum Typical Maximum Unit Function VRX_1 CCONT VR2 CRFU3 DC–voltage 2.67 2.8 2.85 V for Rx part of CRFU 10 15 mVpp 2.8 2.85 V 5 15 mVpp 2.8 2.85 V VRX_2 VSYN_2 VXO VTX CCONT VR5 SUMMA CCONT VR4 VCO’ VCO’s CCONT VR1 VCTCXO CCONT VR7 CRFU3 voltage ripple when on DC–voltage 2.67 voltage ripple when on DC–voltage 2.
PAMS NSE–8/9 System Module Technical Documentation Table 18. AC and DC Characteristics of signals between Baseband and RF (continued) Signal name From To Parameter Minimum AFC COBBA_GJP VCTCXO Voltage 0.046 RXC COBBA_GJP SUMMA Resolution Maximum Unit Function 2.254 V Automatic frequency control t l signal i l ffor VCTCXO 11 bits Load resistance (dynamic) 10 kohm Load resistance (static) 1 Mohm Noise voltage 500 uVrms Settling time 0.5 ms Voltage Min 0.12 0.
PAMS NSE–8/9 System Module Technical Documentation Table 18. AC and DC Characteristics of signals between Baseband and RF (continued) Signal name From To Parameter Minimum TXC COBBA_GJP SUMMA Voltage Min Voltage Max Maximum Unit Function 0.12 0.18 V 2.27 2.
PAMS NSE–8/9 System Module Technical Documentation Table 18. AC and DC Characteristics of signals between Baseband and RF (continued) Signal name From To Parameter Minimum Typical Maximum Unit Function TXQN / TXQP COBBA_GJP SUMMA Differential voltage swing 1.022 1.1 1.18 Vpp DC level 0.784 0.8 0.816 V Differential quadrature phase TX Baseband i l ffor th d signal the RF modulator Differential offset voltage (corrected) +/– 2.0 mV Diff. offset voltage temp. dependence +/– 1.
PAMS NSE–8/9 System Module Technical Documentation Table 18. AC and DC Characteristics of signals between Baseband and RF (continued) Signal name From To Parameter Minimum SCLK MAD2PR1 SUMMA Logic high ”1” Typical Maximum Unit Function 2.0 Vbb V PLL clock Logic low ”0” 0 0.5 V Load impedance 10 kohm Load capacitance 10 Data rate frequency SENA1 FRACT RL MAD2PR1 SUMMA MAD2PR1 CRFU 3.25 RFC MAD2PR1 SUMMA VC(TC)XO MAD2PR1 2.0 Vbb V Logic low ”0” 0 0.
PAMS NSE–8/9 System Module Technical Documentation Table 19. NSE–8/9 Baseband key components Name used in this document Schematic Ref.
NSE–8/9 System Module PAMS Technical Documentation integrated into one ASIC, called the MAD2PR1 chip, which takes care of all the signal processing and operation controlling tasks of the phone. The Baseband architecture supports a power saving function called ”sleep mode”. This sleep mode shuts off the VCTCXO, which is used as system clock source for both RF and Baseband. During the sleep mode the system runs from a 32 kHz crystal. The phone is waken up by a timer running from this 32 kHz clock supply.
PAMS NSE–8/9 Technical Documentation System Module for the control of the RF synthesizer. The COBBA_GJP asic also provides A/D and D/A conversions of received and transmitted audio signals to and from the internal and external audio transducers.
NSE–8/9 System Module PAMS Technical Documentation Data transmission between the COBBA_GJP and the MAD2PR1 is implemented using two serial busses, SERRFI for RF digital data and COBBA_GJP control. PCM for digital audio data. Digital speech processing is handled by the MAD2PR1 asic. Last but not least the COBBA_GJP emits the backlight control signals to the UISWITCH IC, which drives the keyboard– and LCD backlight LEDs. The Baseband supports 3 microphone inputs together with 2 earphone outputs.
PAMS NSE–8/9 Technical Documentation System Module Baseband Functional Description There are four actions that initiate the power up procedure of the phone; 1. pressing the power on/off button 2. connecting a charger to the phone 3. power up initiated by a pulse on BTEMP (DCT3 IBI pulse) 4. power up initiated by RTC Because the power up procedure is somewhat different depending on the initializing action they are described below separately.
PAMS NSE–8/9 System Module 3.1 3.2 3.3 3.4 Technical Documentation MAD takes over the system control the SLEEPX signal control switches to MAD MAD notices the CCONT_INT active MAD reads the CCONT interrupt register, identifies the charger interrupt and starts to control the charging In the end of the power up procedure initialized by adding the charger the phone goes to ”POWER ON ACTING DEAD” state.
PAMS NSE–8/9 Technical Documentation 4.a.4 4.a.5 System Module MCU turns on the keyboard and display lights MCU performs PIN enquiry i.e. checks if PIN code needs to be asked and if yes, asks it 4.b ELSE THE KEYBOARD POWER INTERRUPT IS NOT ACTIVE LONG ENOUGH THEN THE PHONE STARTS POWER DOWN PROCEDURE In the end of this power up procedure the phone is in a state where it is ready for network synchronization and communication with the user.
PAMS NSE–8/9 System Module Technical Documentation asked and if yes, asks it MCU starts communicating with the world 4.6 5. POWER ON/RTC: – BB regulator active – VCXO regulator active – COBBA–analog regulator active – SIM regulator active – MAD controls the system – power on indicated to the user In the end of this power up procedure the phone is in ”POWER ON/RTC” state where it will indicate the alarm to the user by beeps and/or display information.
PAMS NSE–8/9 Technical Documentation 3.2 3.3 System Module CCONT activates power up reset (PURX) signal which disables all regulators (system control switches to CCONT at PURX activation) CCONT powers itself off 4. POWER OFF STATE – all components except CCONT RTC and DC/DC converter are powered off – all resets active There is a delay of 100 us between the expiring of the watchdog and reaching the power off state. During this time CCONT does not accept charger detection nor power on interrupts, i.e.
NSE–8/9 System Module PAMS Technical Documentation phone powers off. The power down procedure can be entered from any operational state. A brutal way for power down is to remove a battery when the phone is powered on. The phone gets warning of this by LOW_BATT detection signal which is connected directly to MAD (CARDDETX) . When MAD realizes that battery is being removed it has 2 – 4 ms time to power down the SIM interface in order to protect the SIM card.
PAMS NSE–8/9 System Module Technical Documentation Clocking Concept This section describes the main clocks in the system. VCXO 13 MHz SINE WAVE SIM CLK CCONT MAD2PR1 3.25 MHz 32 kHz SLEEP CLOCK 13 MHz AFC COBBA_GJP 13 MHz 520KHz PCM PLL 52 MHz GENSIO_0 8 kHz PCM SYNC 3.25 MHz SYNTE CLK Summa DSP 1.083MHz LCD DRIVER osc 16.3KHz Figure 8. Clocking Scheme The system clock in the HD947 phone is 13 MHz. It is generated in the RF VCTCXO circuit.
PAMS NSE–8/9 System Module Technical Documentation Cobba_GJP uses the 13 MHz clock,COBBACLK, coming from MAD2PR1 as a system clock. The 520KHz PCM codec master clock,PCMDClk, and the 8 KHz PCM codec frame synchronization clock,PCMSClk, are the two PCM codec related clocks going from COBBA_GJP to MAD2PR1 . The master clock is used to clock the transfer of the PCM samples between COBBA PCM codec and MAD2PR1 DSP.
PAMS NSE–8/9 Technical Documentation System Module Power up reset, PURX, is the main reset of the system. It is controlled by the CCONT digital part and is released in the power up. PURX is related to the CCONT watchdog which in turn is the main watchdog of the system. CCONT watchdog is controlled by the MCU SW which has to update it at regular intervals. If the CCONT watchdog expires then PURX goes activate and the power of the phone is turned off.
PAMS NSE–8/9 System Module Technical Documentation RF reg. RF SUPPLIES PA SUPPLY VCOBBA LCD VBB COBBA VBB VSIM CCONT PWRONX VBB Vdc_out Vdc_out Vcore VBB PURX Ctrl LED’s Buzzer Vibra VBB UISwitch SIM PWM DC/DC Converter Vcon_1/2 Ctrl VB MAD2PR1 Flash Rom Charge_off Vpp RAM EEProm VBB VBB VBB PSCC_pwm Figure 10.
PAMS NSE–8/9 System Module Technical Documentation The main portion of the power for the PAs during Tx burst are supplied by the output capacitors, C109 – C113, the switcher current being limited to 1.6 A in burst, and 1.0 A in between bursts. The capacitors are recharged in between the Tx bursts, with less current to obtain a better converter efficiency.
PAMS NSE–8/9 System Module Technical Documentation The schottky diode, V101 is only conducting during the small time when power FET conduction inside V105 is shifted. The resistors R131 and R132 forms together with the transistor V109a and R134 a circuit which will shut down the switcher when the battery voltage reaches 1.4V in order not to drain the battery below a limit of insufficient current capability.
PAMS NSE–8/9 System Module Technical Documentation Vsim There is a switched mode supply for SIM–interface. The SIM voltage is selected via serial IO. The 5V SMR can be switched on independently of the SIM voltage selection, but can’t be switched off when VSIM voltage value is set to 5V. Table 21. Electrical characteristics of VSIM and V5V Characteristics Condition Min Typ Max Unit Output voltage VSIM Over temperature Over current 2.8 4.8 3.0 5.0 3.2 5.
PAMS NSE–8/9 System Module Technical Documentation Charging At the phone end there is no difference between a plug–in charger or a desktop charger. The DC–jack pins and bottom connector charging pads are connected together inside the phone. V114a MAD2PR1 PSCC_PWM Vbb R140 Vb R137 PSCC PWM V105 VBat VCH Vchout GND C122 RSSI_adc MAD2PR1 C126 CHARGER Charge_off V–charge_in 1.
PAMS NSE–8/9 System Module Technical Documentation The power switch is controlled according to PWM input via V114a. PSCC_PWM is supplied from the MAD and is different from the external charge control PWM signal, which is supplied by the CCONT. When PSCC_PWM is low, the switch is turned ON and the output current, Iout, equals the charger current , except for the internal PSCC supply consumption. When PSCC_PWM is high, the switch is OFF and the output current is zero or Istart , depending upon Vb.
NSE–8/9 System Module PAMS Technical Documentation If the battery voltage reaches Vstart limit, before the SW has taken control over the charging, the startup current is switched off by the PSCC. Software controlled charging PWM charging (fast charging) is controlled by the MCU software. The sw performs a charger detection and tries to recognize the charger by a mix of charger voltage, and charger current measurement ) via the ADC’s in CCONT.
PAMS NSE–8/9 System Module Technical Documentation Baseband ADC’s The NSE–8/9 Baseband ADC’s are configured completely different compared to conventional DCT3 products. Table 23.
PAMS NSE–8/9 System Module Technical Documentation Battery Voltage The ADC is to be calibrated in production / service, with a one point calibration at 2.7V. Table 25. Battery voltage, ADC properties Parameter min typ Resolution max Unit 10 Conversion error 8.6 Vb range 9.4 0 bits 1024 ADC output values 10.2 mV corresponding to +/– 2 LSB 3.6 V range given by PSCC ADC reading 1023 Vb voltage @ ADC saturation 4.4 4.8 5.2 V Vb ADC resolution 4.3 4.7 5.
PAMS NSE–8/9 System Module Technical Documentation Table 27. ADC reading and NTC resistance vs. temperature T [ C] ADC read R [k ] T [ C] ADC read R [k ] T [ C] ADC read R [k ] –25 899 725.7 20 381 59.3 65 88 9.4 –20 860 525.7 25 327 47.0 70 75 7.9 –15 812 385.7 30 279 37.6 75 64 6.7 –10 758 286.2 35 238 30.2 80 55 5.7 –5 698 214.8 40 201 24.5 85 47 4.8 0 634 162.9 45 171 20.0 90 41 4.1 Table 28.
PAMS NSE–8/9 System Module Technical Documentation Vdc_out voltage Table 30. Switcher output voltage, ADC properties Parameter min Resolution typ max 10 Conversion error Vdc_out range 0 Unit bits 1024 ADC output values 13 mV corresponding to +/– 2 LSB 6.5 V range given by Vdc_out over voltage protection ADC reading 1023 Vdc_out voltage @ADC saturation 6.52 6.65 6.78 V Vdc_out resolution 6.4 6.5 6.6 mV/bit Vbat_adc range 0.
PAMS NSE–8/9 Technical Documentation System Module – AccIF(Accessory Interface) – SCU (Synthesizer Control Unit for controlling 2 separate synthesizer) – UIF (Keyboard interface, serial control interface for COBBA_GJP PCM Codec, LCD Driver and CCONT) – UIF+ (roller/ slide handling) – SIMI (SimCard interface with enhanced features) – PUP (Parallel IO, USART) – FLEXPOOL (DAS00308 FlexPool Specification) – SERRFI (DAS00348 COBBA_GJP Specifications) MAD Power Up Procedures Because MAD2PR1 includes three fu
NSE–8/9 System Module PAMS Technical Documentation MAD FLASH down loading power up The FLASH down loading power up procedure is similar to that of DCT2. The only difference is that instead of external RAM the internal API RAM may be used to store the FLASH down loading program (if the down loading program fits into the API RAM it is stored there, if not then it is stored to external RAM). The procedure is described below. 0.
PAMS NSE–8/9 System Module Technical Documentation 4.2 MCU sets the FBUS TX line low to indicate that it has successfully received the FLASH programming SW, has initialized itself correctly and it is ready to accept a command from FLASH prommer After this power up procedure MCU receives commands from the FLASH programmer and acts accordingly using the FLASH loading SW either in the API RAM or the external RAM.
PAMS NSE–8/9 System Module Technical Documentation Battery removal SIMCardDetX input on MAD is a threshold detector with a nominal input switching level 0.85xVbb for a rising edge and 0.55xVbb for a falling edge. The battery removal detection is used as a trigger to power down the SIM card before the power is lost. V109a pulls SIMCardDetX high, telling the MAD to power down RF, SIM and Baseband, which takes about 2ms.
PAMS NSE–8/9 System Module MCUWrX MCUAD(20:0) MCUAD(20:1) MCUAD(16:0) MAD2PR1 ESysResetX CS RAM WE WE Flash Rom CS 128k x 8 OE OE MCUDa(15:8) ExtMCUDa(7:0) MCUGenIO3 CS Vpp RP MCUDa(7:0) MCUGenIODa(7:0) MCUGenIO0 1M x 16 WP Data Clock MCUGenIO4 SDA EEProm SCL ESysResetX RAMSelX R307 MCURdX MCUGenIO1 ROM1SelX Technical Documentation 16K x 8 WC Figure 16.
NSE–8/9 System Module PAMS Technical Documentation MAD2PR1 interfaces to the RAM via a parallel memory bus which consists of 17 address lines, MCUAd(16:0) and 8 data lines, MCUDA(7:0) both shared with the Flash memory bus. Read and write strobes and two chip selects, one of which is the system reset. EEPROM Memory An EEPROM is used for a nonvolatile data memory to store the tuning parameters and phone setup information.
PAMS NSE–8/9 System Module Technical Documentation Table 32. Flash programming, Vpp, properties Parameter Normal phone operation signal min Vpp 0 typ Ipp leak Aftersales programming Vpp 1.65 max Unit 1.0 V HW protected against programming 0.2 mA Max allowed leakage current from Vpp pin on flash for safe write protection. Phone has 4k7 pull down resistor. 3.
PAMS NSE–8/9 System Module Technical Documentation As opposed to DCT3 only two signals are used for direct regulator control: – VCXOPwr to control VCTCXO supply On/Off – SIMCardPwr to turn SIM card supply on/off All other regulators are controlled via the serial control bus. Which is implemented with the 3 lines CCONTCSX for chip select, GenSIO_1 for data and GenSIO_0 for 1.083MHz clock. The bus is a general purpose bi–directional bus shared with the LCD–driver.
PAMS NSE–8/9 Technical Documentation System Module The Cobba_GJP is a mixed signal IC including the Baseband RF analog interface and the Baseband audio PCM interface. The Cobba converts the down link audio PCM stream from the DSP to analog signals feeding the audio output transducers. The Coba converts the analog audio input from the microphone devices to an uplink PCM bit stream to be feed to the DSP for further processing. The MAD a separate pin for resetting the Cobba.
PAMS NSE–8/9 System Module Technical Documentation Internal Audio Microphone, uplink audio: The internal uplink audio circuitry consists of basically 5 blocks: Page 2– 64 1. The microphone device: Which converts air pressure variations to current variations. The internal microphone is placed in a well in the bottom connector part, it’s connected to the bottom connector by means of mounting springs for automatic assembly. 2. The microphone bias circuitry: MBIAS from Cobba generates a 2.
PAMS NSE–8/9 System Module Technical Documentation Table 33. Internal uplink audio Baseband specifications Parameter min Mic Bias current 100 Microphone sensitivity –2 Internal cobba gain total internal cobba gain typ 42 max Unit 500 uA Max supply by the cobba +2 dB 0dB = 1V/Pa @ 1kHz dB set by MCU SW in cobba register +0.5 dB 300 < f <3400 Hz 25 mV 300 < f <3400 Hz, to not saturate the Cobba input stage with Cobba gain (MCU value) 18 dB below 200mV 18 –0.
PAMS NSE–8/9 System Module Technical Documentation External Audio The external audio of NSE–8/9 is designed only for support of the Janette Accessory program units: – PPH–1 Carkit with and without external microphone HFM–8 – HDC–5 button headset The PPH–1 uses Cobba input MIC1 since to output from PPH–1 is higher there is less gain in the NSE–8/9 Baseband. HDC–5 uses MIC3, since the headset microphone generates a weaker signal there is need for higher amplification in the NSE–8/9 Baseband.
PAMS NSE–8/9 Technical Documentation System Module 4. Conversion: The Cobba GJP ASIC converts the analog audio signal to a PCM bitstream which is supplied to the DSP for further speech processing. The selection between which inputs to use is handled by the MCU through control registers inside Cobba 5. EMC protection: The Low pass filter mad by R231, C257 and R232, C256 improves the immunity towards high frequency signals picked up by the audio accessory cable.
NSE–8/9 System Module PAMS Technical Documentation Audio accessory detection When a jack is plugged into the bottom connector X503 it activates the bottom connector switch, thus opens the connection between R200 and R202 which will make HEADDET pin on MAD go high indicating an interrupt to the SW. When no accessory is present the switch inside the bottom connector X503 is closed and HEADDET is pulled low by R202.
PAMS NSE–8/9 System Module Technical Documentation UI The UISWITCH IC is an integrated switch IC for UI purposes. It includes control switches for buzzer–, vibra– , LED– (display & keyboard) control and two current sinks for LED’s.
PAMS NSE–8/9 System Module Technical Documentation Table 35. Input and output characteristics of the UISwitch IC (continued) Parameter Pin Buzzer FET switch Rdson BUZZER VIBRA nominal current @ VBAT = 3.6V Rvibra (typ.) = 10 VIBRA VIBRA FET switch Rdson VIBRA Symbol Min Ivibra Typ Max Unit 1 120 mA 1 For a complete specification of the UISwitch IC. Backlight 4 LEDs are used for LCD back lighting. They are controlled by the signal LCD_light coming from the Cobba_GJP.
PAMS NSE–8/9 Technical Documentation System Module When the signal , BUZZER, is high, current runs through the buzzer, and when it’s low no current flow. The BUZZ_CNT pin is has an internal pull–down resistor. UISWITCH has a low on–resistance FET switch for the buzzer (pin BUZZER) and an internal protection diode. Vibra, NSE–9 only A vibra alerting device is used for giving silent signal to the user of an incoming call. The device is controlled with by a PWM signal, VIBRA, which is supplied by MAD2PR1.
PAMS NSE–8/9 System Module Technical Documentation – GenSIO_0: Serial data clock, 1.083 MHz from MAD2PR1 (GenSClk) – GenSIO_1: Serial Data from MAD2PR1 (GenSDIO), Data is read on the rising edge of the clock. On every eight clock pulse, the data is transferred from the shift register and processed as 8–bit parallel data. LCDCD is read on the rising edge of every eight clock signal.
PAMS NSE–8/9 Technical Documentation System Module RF The RF module converts the signal received by the antenna to a baseband signal and vice versa. It consists of a conventional superheterodyne receiver and a transmitter for each band and also two frequency synthesizers for the required mixing. The architecture contains two integrated circuits, a CRFU3_D1 and a SUMMA. They are both BiCMOS ASICs, which is a suitable technology for integration of RF functions.
PAMS NSE–8/9 System Module Technical Documentation 13 MHz VCTCXO RX TXI TXQ 13 MHz 116 MHz IQ–Mod 58 MHz 232 MHz IQ–Mod VHF PLL UHF PLL Divider System SUMMA VCO VCO 464 MHz 71 MHz 1942–2067 MHz 232 MHz 116 MHz 1942–2017 MHz f 116 MHz 187 MHz f/2 1992–2067 MHz 1006–1031 MHz CRFU3 1805–1800 MHz 935–960 MHz Figure 20.
PAMS NSE–8/9 System Module Technical Documentation DC Regulators The transceiver has a multi function power management IC, which contains among other functions 7 pcs of 2.8 V regulators. All regulators can be controlled individually with 2.8 V logic directly or through a control register. However, in the chosen configuration of the CCONT, direct control is only used with VR1. The control register is used to switch off the regulators when they are not in use. The CCONT also provides a 1.
PAMS NSE–8/9 System Module Technical Documentation Frequency Synthesizers Both the UHF- and the VHF-VCO are locked with PLLs to a stable frequency source, which is a VCTCXO-module (Voltage Controlled Temperature Compensated Crystal Oscillator). The VCTCXO is running at 13 MHz and is locked to the frequency of the base station by means of an AFC (Automatic Frequency Control). LO to GSM1800 LO to GSM900 Figure 22.
PAMS NSE–8/9 Technical Documentation System Module To preserve the stability of the loop a resistor is included for phase compensation. Other filter components are for sideband rejection. The dividers are controlled via the serial bus. SDATA is for data, SCLK is the serial clock for the bus and SENA1 is a latch enable, which enables storing of new data into the dividers. The UHF-synthesizer is the channel synthesizer, so each step equals the channel spacing (200 kHz).
PAMS NSE–8/9 System Module Technical Documentation Figure 23. Receiver Block Diagram GSM900 Front–End The GSM900 receiver is a dual conversion linear receiver. The front–end, which is located in the CRFU3 RF-, is activated with the band-selection signal (BAND_SEL) set to high-state. The received RF-signal from the antenna is fed via the diplex filter and the duplex filter to the LNA (Low Noise Amplifier) in the CRFU3.
PAMS NSE–8/9 Technical Documentation System Module GSM1800 Front–End The GSM1800 receiver is a triple conversion linear receiver. The received RF-signal from the antenna is fed via the diplex filter, the RX–TX switch and the first RX SAW filter to the LNA in CRFU3. The RX–TX switch is controlled by the band selection signal (BAND_SEL = low) and the supply voltage for the transmitter part (VTX = low). VTX ensures that the switch can not turn to transmit position when the transceiver is in receive mode.
NSE–8/9 System Module PAMS Technical Documentation Next stage in the receiver chain is an AGC-amplifier. It is integrated into the SUMMA. The AGC gain control is analog. The control voltage for the AGC is generated with a DA-converter in the COBBA in baseband. The AGC-stage provides an accurate gain control range (min. 57 dB) for the receiver. After the AGC-stage, the 71MHz IF-signal is mixed down to 13MHz.
PAMS NSE–8/9 System Module Technical Documentation Transmitter The transmitter consists of an IQ-modulator that is common for the GSM900 and the GSM1800 chain, two image rejection upconversion mixers, two power amplifiers and a power control loop. Figure 24. Transmitter Block Diagram Common Transmitter Part The I- and Q-signals are generated by the COBBA in baseband. After the post filtering (RC-network) they are fed into the IQ-modulator in the SUMMA.
NSE–8/9 System Module PAMS Technical Documentation GSM900 Transmitter The IQ–modulator generates a modulated TX IF-signal centered at 116 MHz, which is the VHF-synthesizer output divided by four. The TX-amplifier in the SUMMA has two selectable gain levels. The output, which is balanced, is set to maximum via a control register in the SUMMA. After the SUMMA there is a bandpass LC-filter for reduction of noise and harmonics before the signal is upconverted to the final TX-frequency.
PAMS NSE–8/9 Technical Documentation System Module GSM1800 Transmitter The IQ–modulator generates a modulated TX IF-signal centered at 232 MHz, which is the VHF-synthesizer output divided by two. The TX-amplifier in the SUMMA has two selectable gain levels. The output (single-ended) is set to maximum via a control register in the SUMMA. After the SUMMA there is a SAW filter for reduction of noise and harmonics before the signal is fed for upconversion into the final TX-frequency in the CRFU3.
NSE–8/9 System Module PAMS Technical Documentation After the TX/RX switch the signal is fed to the diplexer. The TX/RX switch is set to transmit position with BAND_SEL = low and VTX = high. There is a directional coupler connected between the PA output and the input of the TX/RX switch to provide feedback for the power loop.
PAMS NSE–8/9 Technical Documentation System Module AGC The purpose of the AGC-amplifier is to maintain a constant output level from the receiver. To accomplish this, pre-monitoring is used. This pre-monitoring is done in three phases and determines the settling time for the RX AGC. The receiver is switched on approximately 150 s before the burst begins and DSP measures the received signal level.
PAMS NSE–8/9 System Module Technical Documentation When the transceiver is in sleep mode and ”wakes” up to receive mode, there is only about 5 ms for the AFC-voltage to settle. When the first burst arrives the system clock has to be settled to +/- 0.1 ppm frequency accuracy. The VCTCXO-module requires about 4 ms to settle into the final frequency.
PAMS NSE–8/9 System Module Technical Documentation ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ
NSE–8/9 System Module PAMS Technical Documentation ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1. SDATA Synth Data 2. SCLK 3.
PAMS NSE–8/9 System Module Technical Documentation Parts Lists System Module (0201234) (EDMS V 3.
PAMS NSE–8/9 System Module R144 R200 R202 R205 R206 R207 R208 R212 R214 R215 R216 R217 R218 R219 R220 R223 R225 R226 R227 R228 R230 R231 R232 R300 R301 R302 R303 R307 R309 R310 R311 R312 R313 R315 R317 R318 R319 R413 R415 R418 R420 R421 1430820 1430816 1430804 1430734 1620031 1620025 1620019 1430796 1430744 1620031 1620103 1430762 1430762 1430762 1430762 1430778 1430215 1430816 1430718 1430718 1430784 1430710 1430710 1430778 1430804 1430778 1430778 1430770 1430796 1430770 1430812 1620017 1430726 1430690
PAMS NSE–8/9 System Module Technical Documentation R422 R423 R424 R500 R501 R502 R503 R504 R505 R506 R507 R508 R509 R510 R511 R512 R513 R514 R515 R516 R518 R519 R520 R521 R522 R601 R602 R603 R604 R605 R606 R607 R608 R609 R610 R611 R612 R614 R619 R700 R701 R702 1430710 1430770 1430718 1430772 1430772 1430762 1430738 1430708 1430738 1430726 1430718 1430718 1430726 1430700 1430744 1430744 1430744 1430700 1430744 1430726 1820037 1430691 1430691 1430691 1430691 1430700 1430728 1430754 1430754 1430754 1430832
PAMS NSE–8/9 System Module R703 R704 R705 R706 R707 R708 R709 R710 R711 R712 R713 R714 R715 R716 R717 R718 R719 R721 R722 R724 R725 R726 R727 R728 R729 R730 R731 R732 R733 R734 R735 R736 R737 R741 R742 R743 R745 R765 R766 C100 C101 C102 1430690 1430778 1430790 1430754 1430784 1620019 1430710 1620019 1430762 1430726 1430710 1620019 1430788 1430740 1430734 1430734 1430724 1430734 1620031 1430754 1430770 1430784 1430758 1430754 1430790 1430772 1430762 1620103 1430792 1430726 1430778 1430804 1430726 1430700
PAMS NSE–8/9 System Module Technical Documentation C103 C104 C105 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 2320481 2312401 2320546 2320620 2320546 2611689 2611689 2611689 2611689 2611689 2320536 2611725 2320584 2610003 2320546 2320546 2610003 2320779 2320546 2312211 2320131 2320538 2320546 2320546 2320546 2320546 2320779 2320546 2312403 2320546 2610003
PAMS NSE–8/9 System Module C148 C149 C150 C151 C152 C153 C154 C155 C156 C158 C162 C163 C165 C166 C167 C168 C169 C201 C202 C203 C204 C205 C206 C207 C208 C209 C210 C213 C215 C216 C218 C219 C220 C221 C222 C223 C224 C225 C226 C227 C229 C232 2320560 2320915 2320546 2320620 2610003 2320546 2320783 2320546 2320546 2320584 2320576 2320107 2320546 2320546 2320779 2320546 2320546 2610205 2320546 2610205 2320546 2320783 2610205 2320783 2320783 2320546 2320783 2320783 2320584 2320584 2320546 2320546 2610205 2320546
PAMS NSE–8/9 System Module Technical Documentation C233 C234 C235 C236 C242 C243 C244 C247 C248 C249 C250 C251 C256 C257 C258 C259 C301 C304 C305 C306 C307 C313 C314 C316 C317 C400 C401 C402 C500 C501 C503 C504 C506 C507 C508 C510 C511 C512 C513 C514 C515 C516 2320546 2320546 2320584 2320584 2320546 2320546 2320805 2320620 2610003 2320546 2320546 2320546 2320584 2320584 2320783 2320783 2320584 2309570 2320546 2320546 2312401 2312401 2320546 2312401 2320584 2312401 2312410 2320546 2320546 2320546 2320546
PAMS NSE–8/9 System Module C519 C521 C522 C523 C524 C525 C526 C600 C601 C602 C603 C604 C605 C606 C607 C608 C609 C611 C612 C613 C615 C616 C617 C618 C619 C621 C622 C623 C624 C625 C626 C627 C629 C631 C632 C633 C634 C635 C636 C637 C638 C639 2312401 2320546 2320584 2320538 2320620 2320620 2320584 2320518 2320540 2320530 2320540 2320550 2320546 2320546 2320538 2320520 2320522 2320546 2320805 2320546 2320584 2320550 2320556 2320556 2320524 2320546 2320564 2320805 2320805 2320805 2320546 2320518 2320518 2320536
PAMS NSE–8/9 System Module Technical Documentation C640 C641 C642 C643 C645 C646 C647 C648 C649 C700 C701 C702 C703 C704 C705 C706 C707 C708 C709 C710 C712 C713 C714 C715 C716 C717 C718 C719 C720 C721 C722 C723 C724 C725 C726 C727 C728 C729 C730 C731 C732 C733 2320536 2320550 2320532 2320518 2320564 2320580 2320620 2320584 2320532 2320546 2320534 2320560 2320530 2320534 2320546 2320584 2320584 2320556 2320556 2320584 2320530 2320568 2320546 2320620 2320584 2320526 2320584 2320568 2320562 2320584 2312401
NSE–8/9 System Module C734 C735 C736 C737 C738 C739 C740 C741 C742 C743 C744 C745 C746 C747 C748 C749 C750 C751 C752 C753 C754 C755 C756 C757 C760 C761 C762 L100 L101 L102 L103 L105 L106 L200 L201 L202 L203 L500 L502 L503 L505 L506 2320560 2320560 2320546 2312401 2320584 2320584 2310209 2320584 2312211 2320524 2320560 2320524 2320570 2320546 2320091 2320516 2312401 2320546 2320564 2320564 2320620 2320564 2320620 2320584 2320584 2320544 2312401 3203705 3203705 3640477 3203717 3640035 3203709 3640035 364003
PAMS NSE–8/9 Technical Documentation L600 L601 L602 L603 L604 L605 L606 L607 L608 L609 L610 L611 L612 L613 L614 L615 L616 L617 L618 L620 L700 L701 L702 L703 L704 L705 L707 L708 L709 L710 B100 B400 G700 G701 G702 F100 Z500 Z501 Z502 Z503 Z504 Z505 3643037 3643037 3645005 3645009 3645035 3645017 3645193 3645181 3645121 3645151 3645151 3645017 3645179 3645181 3645229 3203709 3646055 3645131 3645035 3640035 3645163 3645031 3641601 3641622 3641622 3645161 3645029 3641541 3645195 3203709 4510237 514R029 43501
NSE–8/9 System Module Z600 Z601 Z602 Z603 Z700 Z701 Z702 T600 V101 V103 V104 V105 V108 V109 V112 V200 V202 V207 V301 V400 V401 V402 V403 V404 V405 V406 V409 V410 V412 V413 V500 V702 D300 D301 D302 D303 D700 N100 N101 N114 N200 N400 4511097 4511015 4511103 4511087 4511109 4510009 4511085 3640413 4110065 4210215 4110067 4340669 4219929 4219904 4113651 4113651 4219904 4113651 4113671 4864461 4864461 4864461 4864461 4864461 4864461 4864461 4864461 4110601 4864461 4864461 4110079 4210100 4370489 4340585 434039
PAMS NSE–8/9 Technical Documentation N500 N501 N502 N503 N600 N700 N702 S416 X100 X101 X102 X501 X504 A600 A601 4350177 4350171 4340263 4219941 4370483 4370351 4340335 5219005 5409107 5409109 5409109 5409109 5409111 9517025 9517024 9854307 Issue 1 07/99 System Module IC, pow.amp. 3.5 V IC, pow.amp. 3.5 V IC, RF amp.21DB/900MHZ Transistor x 2 Crfu3 rf asic gsm/pcn bf tqfp–48 Summa v2 rx,tx,pll,pcontr. tqfp48 IC, regulator TK11228AM IC, SWsp–no 30vdc 50ma smSW SM, sim conn 2x3pol p2.54 h=1.
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