User Guide

RM-11
Troubleshooting - Baseband CC Technical Documentation
Page 12 ©2004 Nokia Corporation Confidential Issue 1 02/2004
Figure 4: 19.2 MHz analog
RFConvClk (19.2 MHz Digital)
The UPP distributes the 19.2 MHz Clk to the internal processors, DSP, and MCU, where
SW multiplies this clock by seven for the DSP and by two for the MCU.
Figure 5: 19.2 MHz digital