User Guide

CCS Technical Documentation System Module

RH-48

resonator. The VCO operates at two times the common 183.6 MHz RX IF frequency. A

band-switch signal, Band_Sel, is used to select the band of operation for the UHF VCO.

The synthesizer is a dual-modulus prescaler type, and utilizes a phase detector with a

charge pump that signals or sources currents, depending upon the phase difference

between the detector input signals. The width of the pulses depends on the phase differ-

ence between the signals at input of the phase detector. The main divider, auxiliary

divider, and reference divider are programmable through the serial interface to Yoda.

The RX VHF Synthesizer generates 367.2 MHz.

VCTCXO - System Reference Oscillator

The VCTCXO provides the frequency reference for all the synthesizers. It is a voltage-con-

trolled, temperature-compensated, 19.2MHz crystal oscillator that can be pulled over a

small range of its output frequency. This allows for an AFC function to be implemented

for any frequency accuracy requirements. This is done by DSP processing of received I/Q

signals.

Closed loop AFC operation allows very close frequency tracking of the base station to be

done in CDMA mode. This will enable the unit to track out aging effects and give the

required center frequency accuracy in cellular band.

The most practical way of clock distribution is driving all three chips (UHF PLL, Yoda, and

Jedi) directly from the VCTCXO. An internal buffer is used to drive the UPP in order to iso-

late the UPP’s digital noise from the VCTCXO, which prevents contamination of the

19.2 MHz reference onto the PLL chips of the system. Since the VCTCXO output is a sine-

wave, such clock distribution will not cause any clock signal integrity problems, even for

relatively long traces (what might occur in case of a digital square waveform with fast

transition times). The VCTCXO output is AC, coupled to Yoda, Jedi, UHF PLL, and the digi-

tal ASICs (see the following figure) to eliminate DC incompatibility between those pins.

Figure 10: VCTCXO clock distribution