User Guide

PAMS Technical Documentation Data Module RL7

Company Confidential TME-3

Issue 4 12/03 Nokia Corporation. Page 25

tion. The LNA amplified signal is fed to 2nd RX bandpass RF-SAW filters. Both 2

bandpass RF-SAW filters comprise un-bal/bal configuration to get the balanced (bal-

anced) feed for Hagar.

Discrete LNAs have three gain levels. The first one is max. gain, the second one is about -

30dB(GSM1800) and -25dB(EGSM900) below max. gain and the last one is off state. The

gain selection control of LNAs comes from HAGAR IC.

Differential RX signal is amplified and mixed directly down to BB frequency in HAGAR.

Local signal is generated with external VCO. The VCO signal is divided by 2 (GSM1800) or

by 4 (E-GSM900). PLL and dividers are in HAGAR-IC.

From the mixer output to ADC input RX signal is divided into I- and Q-signals. Accurate

phasing is generated in LO dividers. After the mixer DTOS amplifiers convert the differen-

tial signals to single ended. DTOS has two gain stages. The first one has constant gain of

12dB and 85kHz cut off frequency. The gain of second stage is controlled with control

signal g10. If g10 is high (1) the gain is 6dB and if g10 is low (0) the gain of the stage is

-4dB.

The active channel filters in HAGAR provides selectivity for channels (-3dB @ +/-91 kHz

typ.). Integrated base band filter is active-RC-filter with two off-chip capacitors. Base-

band filter consists of two stages, DTOS and BIQUAD. DTOS is differential to single-ended

converter having 8dB or 18dB gain. BIQUAD is modified Sallen-Key Biquad.

Integrated resistors and capacitors are tunable. These are controlled with a digital con-

trol word. The correct control words that compensate for the process variations of inte-

grated resistors and capacitors and of tolerance of off-chip capacitors are found with the

calibration circuit.

Next stage in the receiver chain is a AGC-amplifier, also integrated into HAGAR. AGC has

digital gain control via serial mode bus. AGC-stage provides gain control range (40 dB,

10 dB steps) for the receiver and also the necessary DC compensation. Additional 10 dB

AGC step is implemented in DTOS stages.

DC compensation is made during DCN1 and DCN2 operations (controlled via serial bus).

DCN1 is carried out by charging the large external capacitors in AGC stages to a voltage

which cause a zero dc-offset. DCN2 set the signal offset to constant value (VrefRF_02

1.35 V). The VrefRF_02 signal is used as a zero level to RX ADCs.

Single ended filtered I/Q-signal is then fed to ADCs in BB. Input level for ADC is 1.45 Vpp

max.

Transmitter

Transmitter chain consists of two final frequency IQ-modulators for upper and lower

band, a dual power amplifier and a power control loop.

I- and Q-signals are generated by baseband. After post filtering (RC-net work) they go

into IQ-modulator in HAGAR. LO-signal for modulator is generated by VCO and is divided