User Guide

TME-3
Disassembly and Troubleshooting PAMS Technical Documentation
Page 40 Nokia Corporation. Issue 3 10/03
Timing diagram
Figure 37: Timing diagram
0. VBAT below V
MSTR
. UEM in NO_SUPPLY or BACK_UP mode depending on the status
of the back-up battery
1. VBAT appears => VBAT > V
MSTR+
(master reset threshold): Bandgap, RC-osc and
start-up logic starts. Time delay DELAY1 starts (T
d1
).
2. DELAY1, 20ms, elapses. UEM in RESET mode
3. VBAT rises above Vcoff+ threshold: Enable regulator reference buffers, time delay
DELAY2 starts (200ms)
4. DELAY2 elapsed: Enable VFLASH1 regulator, DELAY3 (500us) starts
5. DELAY3 elapses: ENABLE VIO, VCORE, VANA and VR3 regulators. DELAY4 starts.
6. DELAY4 elapses: Release PURX. UEM in ACTIVE mode. RF regulators can be enabled
through register writing.