User Guide
Table Of Contents
- Block Diagram
- Block Diagram of System Section (Version 9.0)
- Circuit Diagram of CTRLU Section (Version 9.0)
- Circuit Diagram of PWRU Section (Version 9.0)
- Circuit Diagram of DSPU Section (Version 9.0)
- Circuit Diagram of Audio Section (Version 9.0)
- Circuit Diagram of ASIC Section (Version 9.0)
- Circuit Diagram of RFI Section (Version9.0)
- Circuit Diagram of Receiver Section (Version 9.0)
- Circuit Diagram of Transmitter Section (Version 9.0)
- Layout Diagram of DB1 side 1 (Version 9.0)
- Layout diagram of DB1 side 2 (Version 9.0)
- System Module
- MAIN TOC

SYSTEM MODULE DB1
9701TJE
8–47
NHB–2
Technical Documentation
Copyright Nokia Mobile Phones
UHF
VCO
PLL
VHF
VCO
VCTCXO
+6 V
CRFCONT
+4.5V
TXI
TXQ
AFC
RXI
RXI
CODEC
DIV ENAB
ENAB
ENAB
RFI2
CODEC
ENAB
DBUS
MCU
A/D
DSP
RFI
MCU
RF–BLOCK
CRFRT
KEYBOARD
XEAR
LIGHTS
DISPLAY
TXIP
TXIN
TXQP
TXQN
SIO1
LN
MCU/DSP
MAILBOX
MDA
RX TX
CONTROL
MFI
KEYBOARD
IF
LCD DRIVER
IF
DSP
IF
MCU
IF
POWER
SUPPLY
VL1 VL2
EEPROM
8k x 8
EPROM
(FLASH)
RAM
32k x 8
CLOCK GENERATION
VBATDET
LOCAL
NETWORK
DEV
DEVICE
CONTROL
LOC
LOCALS
CONTROL
OS
OPERATING
SYSTEM
HW
HW
DRIVERS
DSP
DSP
CONTROL
CS
CELLULAR
SYSTEM
DDI
DATA DEVICE
INTERFACE
UI
USER
INTERFACE
JCONN
CHARGE
CONTROL
CHARGER
RX
DETECTION
DECRYPTION
DEINTER–
CHANNEL SPEECH
ADDRESS BUS
DATA BUS
CHANNEL
INTER–
ENCRYPTION
BURST
SIO
I/Q
CLOCK
CONTROL
XMIC
MICRO–
EARPHONE
PHONE
BUZZER
SERIAL BUS
MBUS
MBUS
INTERFACE
BUS
IF
IF
ASIC
RFICLK
DBUS
INTERFACE
RAM
32k x 16
GENER
TX POWER
CONTROL
HD851 BLOCK DIAGRAM 25.4.1995 / PeH
UI
HOOK
SIO
SIDETONE
WD
VIBRA
BATTERY
57.8 kbaud
TXC INT 2
INT 2
INT 2
RXQ
f
f/2
BIAS
CTI
RX
BUFFER
MODULATOR
(PART OF CTI)
TXPWR
RXPWR
SYNTE
CONTROL
FLASH
97.2ks/s
97.2ks/s
97.2ks/s
1ks/s
48.6ks/s
48.6ks/s
f
f/4
CLk
CLkS
CLk
BUS
ENAB
RFI
CLk
DIV
CONTROL
A/D
AGC
SIO2
VA1 VA2 VREF
PWM
DBUS
CLKS
RXQ
RFI2CLK
DATA CLK 512kHz
DIV
PDATA0
D2CA
1024k * 8
SYNTHPWR
TXL
26MHz
TXP
VC
BTYPE
TBAT
TRF
13MHz 135.4KHz
DSP
CLK
60,2MHz
CLK 512kHz
SYNC 8kHz
CALL LED
TBAT
BTYPE
SIO
9600baud
UIM
CARD
IF
UIM
CARD
UIM
POWER
D/A
DIV
DIV
SYNC CLK 8kHz
VITERBI
SENA1
SCLK
SDATA
CODER
CLkS
512kHz
8kHz
13MHz
135,4kHz
512kHz
8kHz
26MHz
26MHz
MCUCLK
CLK 512kHz
SYNC 8kHz
PWR KEY
90 deg
+6V
–4V
Batt.volt.
TXL
DET0
TX 1850–1910MHz
RX 1930–1990MHz
VCXO
313MHz
87MHz
clipped sinewave
1650–1710MHz
13MHz
+4V5_TX
step AGC
TX
LEAVING
DECODER DECODER
SPEECH
CODER
CODER
LEAVING
BUILDING
Block Diagram










