User Guide

PAMS
System Module DB6
NHB–3
Technical Documentation
Original 26/97
Page 4–33
Signal name Signal description To
PCMCOSYCLKX Bit sync clock, inverted DSPU
DCLK DBUS data clock System conn
DSYNC DBUS bit sync clock System conn
DBUSCLK DBUS data clock DSPU
DBUSSYNC DBUS bit sync clock DSPU
UIMCLK UIM data clock UIF
VUIM UIM power control UIF
ROMSELX Chip select for the FLASH memory CTRLU
EROMSELX Chip select for the EEPROM memory CTRLU
BENA Power supply to headset adapter System conn
RAMSELX Chip select for the SRAM memory CTRLU
ROMAD18 Rom address 18, (paging) CTRLU
COL(3:0) Lines for keyboard column write UIF
External Signals and Connections, Bidirectional
Signal name Signal description To/From
DSPDA(15:0) 16–bit data bus DSPU
MCUDA(7:0) MCU’s 8–bit data bus CTRLU
RFIDA(11:0) 12–bit data bus RFI
UIF(6:0) LCD–controller control and keyboard UIF
read bus
UIMDATA Serial data to UIM UIF
Block Description
PSL+ supplies the reset to the ASIC at power up. The ASIC starts the clocks to
the DSP and the MCU. After about 20uS the ASIC releases the resets to all
circuitry. MCU and RFI reset is released after 256 13 MHz clock cycles. DSP
reset release time from DSP clock activation can be selected from 0 to 255
13 MHz clock cycles. In our case 255 is selected. UIM reset release time is ac-
cording to DCS1900 UIM specifications.
The RFC buffer buffers the 26MHz clock from the VCTCXO to the ASIC. In the
ASIC the clock is further buffered and divided for the MCU, RFI, UIM. It also
generates main and sync clocks for audio codec, DSP‘s SIOs and DBUS. The
clock outputs can be disabled in order to save current when the clock is not
needed. Also the DSP oscillator can be stopped by the ASIC.