User Guide

PAMS
System Module DB6
NHB–3
Technical Documentation
Original 26/97
Page 4–16
Circuit Description
Normal operation:
1. MCU tests DSP
2. MCU updates ASIC watchdog timer (> 2Hz)
3. MCU pulses the XPWROFF input on the PSL+ (about 2Hz)
Failed operation:
4. ASIC resets MCU and DSP after about 0.5 s failure
5. PSL+ switches power off about1.5 s after the previous XPWROFF pulse
Power Distribution Diagram
LCD Driver
PCM
CODE
C
MCU
512K x
8
FLASH
32K x
8
SRAM
LCD
E
2
PROM
8K x 8
UIF–module
ASIC
MCU
RFI
LCD
RF
UIF–module
PSL+
VBATT
VCHAR
VL1
VL2
VA1
VA2
VREF
VA1
VL2
VL1
VA2 VL1
VBATT VREF
VA1
VREF VL1
VL1
VL1
VL1
VL2
DSP
32Kx1
6
SRAM
VBATT
VL1
VF
FLASH
BOX
VF
VL1
VL2
Circuit Description
PSL+ control supply voltages. VL1 and VL2 are supply voltages to the logic cir-
cuits. VA1 and VA2 are supply voltages to the audio circuits. VREF is A/D con-
verter and RF reference voltage. VBATT is fed directly to the circuits which
need higher operation voltage and more current like RF transmitter and UIF
backlight. VF is flash programming voltage, which is fed from flash box.
PSL+ output voltages are active, when PSL+ is in power on state.