User Guide

PAMS
System Module DB6
NHB–3
Technical Documentation
Original 26/97
Page 4–14
– 8 kHz syncronisation clock for data transfer between the DSP and
the codec.
– 512 kHz clock and 8 kHz sync. clock for the DBUS data transfer.
The DSP has its own crystal oscillator which can be turned off and on by the
ASIC. The DSP uses differential sinusoidal clock. The frequency is 60.2 MHz.
The MCU generates 8 kHz clock to the codec for the control data transfer.
In the idle mode all the clocks can be stopped except 26 MHz main clock com-
ing from the VCTCXO.
Reset and Power Control Diagram
ASIC
MCU
RFI
PSL+
Reset in
Vcc
XRES reset in
reset in
XPwrOff
approx 2Hz
XPWRON
XPWRON
Reset Out
Reset Out
resetreg
DSP
VL1
UIMRESET
Circuit Description
There are three different ways to switch power on:
– Power key pressing grounds the XPWRON line. The PSL+ detects
that and switches the power on.
– Charger detection on PSL+ detects that charger is connected and
switches power on.