User Guide

Technical Documentation
NHD–4
System Module
P.A.M.S
Page 4–9
Original 11/97
CDSB ASIC Block
Table 6. CDSB ASIC Block Connections
Signal Name Type Notes
XPWR_
RESET
IN Master reset FROM PSL+ 3
XSYS_RESET OUT System Reset
OSC_OUT IN 32KHz Clk input
OSC_IN IN 32KHz Clk input
CDRFI_SI OUT CDRFI Serial Data In
CDRFI_SO IN CDRFI Serial Data Out
CDRFI_SEN OUT CDRFI Serial data ENABLE
CDRFI_SCLK OUT CDRFI Serial data CLocK
CDRFI_9.8M OUT CDRFI 9.8 MHz clock
15.36M_IN IN 15.36MHz Clk IN
9.83M_IN IN 9.83MHz Clk IN
TXD(7:0) I/O CDRFI TX Data
CDRFI_RWSEL OUT CDRFI Read/Write SELect
CDRFI_IQSEL OUT CDRFI Tx IQ SELECT
RXQ IN CDRFI RX Quadrature–phase data
RXI IN CDRFI RX In–phase data
DAFOUT IN CDRFI DAF INput
GATE OUT CDRFI
VCO_EN OUT CDRFI
DSP_CLK OUT 7.68 MHz Clk to DSP
DSP_INT0 OUT DSP Maskable Interupt 0
DSP_INT1 OUT DSP Maskable Interupt 1
DSPAD IN DSP Address Bus
DSPDA I/O DSP Data Bus
DSP_RXW IN DSP Read / Write Select
XDSP_STRB IN DSP Master Strobe
XDSP_DS IN DSP Data Strobe
DSP_SYNC OUT Frame Sync
DSP_MCLK OUT CLK
Codec_FS OUT Frame Sync
Codec_MCLK OUT CLK
MCU_CLK OUT 15.36 MHz Clk to MCU
MCUAD(19:0) IN MCU Address Bus