User Guide

Technical Documentation
NHD–4
System Module
P.A.M.S
Page 4–5
Original 11/97
Baseband Block Connections
Below is a list of the functional blocks of the baseband architecture:
– Power Supply Charging Logic Device (PSL+3)
– Microcomputer Unit (MCU)
– MCU External Memory –
Electrically Eraseable Programmable Read Only Memory (EE-
PROM)
Static Random Access Memory (SRAM)
Flash Memory
– Digital Signal Processor (DSP)
– DSP External Memory –
Static Random Access Memory (SRAM)
– CDSB ASIC
– CDMA RF to BB Interface (CDRFI)
– Audio Coder/Decoder (CODEC)
Internal Signals and Connections
Power Block
Table 1. Power Block Connections
Signal Name Type Notes
XPWRON IN PWR on switch
XPWROFF IN Power off control
VBATT IN Battery voltage
VCHAR IN Charging voltage
VOLTLIM IN Voltage Limiting of charging while call is in prog-
ress.
5VOFF IN voltage reg control –ON / OFF
VCHRGPWM IN PWM for controlling battery charging.
XPWR_
RESET
OUT Master reset
VL1 OUT Logic supply voltage 1.
VL2 OUT Logic supply voltage 2.
VL3 OUT Logic supply voltage 3.
VA1 OUT Analog supply voltage 1.
VA2 OUT Analog supply voltage 2.
VREF OUT Reference voltage
VL5VOLT OUT Logic supply voltage for MBUS