User Guide

Technical Documentation
NHD–4
System Module
P.A.M.S
Page 4–36
Original 11/97
9.8304 MHz Synthesizer
The CDCONT IC (N201) contains a PLL frequency synthesizer which
generates a 9.8304 MHz oscillation used to clock the baseband modules
of the phone. The 15.36 MHz VCTCXO is used as the reference
oscillation. VRXD_C (VRXD) supply biases the PLL at pin 29 of N201 via
R212, decoupled with C221 and C222. There should be approximately
4.15 V on Pin 29. The loop filter of the PLL is external to the CDCONT
IC, comprised of R213, R214, C209, C210, and C211. The internal VCO
input, pin 38 should have approximately 1.60 V on it.
In CDMA operation the bias current to the final PA stage (V113) is dynam-
ic. Bias current is set such that the CLY–10 (V113) final PA stage will
draw 100 mA for up to 10 dBm of CDMA TX output power. Above 10
dBm of output the bias changes, ramping up to a maximum draw of 250
mA achieved at 23 dBm of output power. The slope of this ramp is de-
fined as the TXB Slope. The 250 mA current bias is maintained for power
output greater than 23 dBm. This feature is referred to as Dynamic TXB.
The following graph depicts the dynamic relationship between CDMA out-
put power and CLY–10 (V113) bias current.