User Guide

Technical Documentation
NHD–4
System Module
P.A.M.S
Page 4–30
Original 11/97
Synthesizer Functional Description
Introduction
The synthesizer module generates the oscillations necessary for the
operation of the phone. It provides the clock signal for digital ICs and it
creates the UHF and VHF oscillations needed to up convert and down
convert the baseband signals to RF frequencies. There are three
synthesizers in the NHD–4 phone. Only two will be discussed here, the
UHF and 180 MHz VHF. The third, a 9.8304 MHz clock oscillator, is
discussed in the CDCONT/AGC Functional Description.
The UHF and 180 MHz VHF oscillations are generated by phase lock
loops. The 15.36 MHz VCTCXO (G300) is the reference oscillator for all
frequency synthesis.
PLL IC (N300)
The core of the NHD–4 synthesizer is the PLL IC (N300). This IC
supports two independent PLL circuits, both of which are used in NHD–4.
The primary synthesizer is used to generate the tunable UHF LO. The
secondary synthesizer generates a constant 180 MHz VHF signal. The IC
is programmed by three lines; RX_LE, DATA, and CLK. There are three
DC voltage supply pins on this device. Pins 4 and 5 should be
approximately 3.15 V, and Pin 18 should be 4.15 V.
The VCTCXO Clock (G300)
A 15.36 MHz VCTCXO (G300) creates the common reference frequency
(clock) for the synthesizers, as well as the remainder of the phone.
Biasing this device requires 3.60 V on pin 4, V
DD. The 15.36 MHz clock
signal is routed to the PLL IC (N300) pin 8, CDRFI IC (N700), and
CDCONT IC (N201).
The UHF Synthesizer
The operating frequency range of the UHF synthesizer is 914.01 to
938.97 MHz, or AMPS channels 990 to 799. This synthesizer has two
modes of operation, Normal and Fast. Normal mode is the default, while
Fast mode allows the synthesizer to lock to frequency faster. Fast mode
is activated with the Fast line held active high. The output of the UHF
passive loop filter is a DC voltage of 1.0 to 3.0 volts that tunes the VCO
(G301) at the “C” pin. The VCO (voltage controlled oscillator) (G301)
generates the UHF LO. The “B” pin of the VCO should be biased with
approximately 4.25 V, supplied from VRXS via R808. VRXS should be
approximately 4.15 V at R808 when the phone is in AMPS mode.
The output RF power from the VCO is routed to two gain stages and back
to the PLL IC pin 6 to close the phase locked loop. The two gain stages
amplify the UHF LO signal and provide it to the RX and TX modules
respectively.