User Guide

Technical Documentation
NHD–4
System Module
P.A.M.S
Page 4–21
Original 11/97
Bias voltage to the CDAGCT IC is critical. The bias voltage at pins 6, 14,
17, 20, 21, 26, and 29 should always be approximately 3.9 to 4.0 V.
Should it drop to low, or become to great, the CDAGCT IC will not operate
properly. A loss of gain may also occur. The VTXT regulator supplies
voltage to the CDAGCT IC. VTXT should stay constant at 5.3 V in both
AMPS and CDMA operation. The R103, R104 resistor network together
with V115 keep the bias to the CDAGCT IC fixed at about 3.9 V.
AT–109 Variable Attenuator (V106)
The AT–109 (V106) is an attenuation stage in the RF path immediately
following the CDAGCT IC (N100). The VC voltage to pin 5 of this device
sets the level of attenuation. For minimum attenuation in CDMA mode
(maximum output power) VC will be 3.25 V. For maximum attenuation in
CDMA mode VC is 1.50 V. In AMPS TX mode VC will be approximately
4.35 V throughout the entire dynamic range of the transmitter output.
VTXS biases the AT–109 at pin 4. It should be 4.4 V for both AMPS and
CDMA operation.
SAW Filter (Z100)
This Surface Acoustic Wave (SAW) filter provides rejection in the RX band
(869 to 894 MHz).
1st and 2nd Gain Stages (V110, V111)
The first gain stage V111 should be biased with approximately 3.85 V on
the collector and 0.73 V on the base. V100 acts as a switch, sourcing
current to V111 when the bias voltage on the emitter resistor goes high to
approximately 4.7 V. V100 should have approximately 3.85 V on its
emitter (pin 3) and 3.30 V on its base (pin 2).
The second gain stage V110 should be biased with approximately 2.70 V
on the collector and 0.73 V on the base. V100 acts as a switch, sourcing
current to V110 when the bias voltage on the emitter resistor goes high to
approximately 4.7 V. V100 should have approximately 2.70 V on its
emitter (pin 6) and 3.30 V on its base (pin 5).
SAW Filter (Z101)
This Surface Acoustic Wave (SAW) filter provides rejection in the RX band
(869 to 894 MHz).
3rd Stage Amplifier (V112)
The third gain stage (V112) is a BJT amplifier in the common emitter
configuration. This stage provides of gain to the TX chain, providing drive
power to the final PA stage, V113.
The third gain stage V112 should be biased with approximately 6.0 V on
the collector and 0.7 V on the base. The dual transistor package V108
acts as a switch, sourcing current to V112 when the voltage to the emitter
resistors goes high to approximately 6.2 V. V108 should have
approximately 6.0 V on its pin 6 emitter and 5.5 V on both bases (pins 2
and 5).