User Guide

Technical Documentation
NHD–4
System Module
P.A.M.S
Page 4–20
Original 11/97
TX PA Bias Control (Dynamic TXB)
The TXB PDM is used to tune the PA bias current. This PDM voltage
interacts with, VTXS, VNEG and an op–amp internal to the CDCONT IC
(N201) to produce VGG. VGG is the negative voltage supply to the gate
of the CLY–10 PA (V113). As VGG changes, so does the bias current.,
and thus the gain. For minimum bias, the 100 mA case the TXB PDM
voltage will be approximately 1.50 V, and VGG will be about –2.35 V. For
maximum bias, or the 250 mA case, the TXB bias will be approximately
1.40 V and VGG will be about –2.00 V. A chart better depicts this data.
Below are some typical voltages and PDM values for this scenario.
Bias Case CDMA TX
Output Pow-
er
(dBm)
TXB PDB
at C703
(V)
TXB PDM
(decimal val-
ue)
VGG
at C202
(V)
Minimum – 100 mA <= 10 1.19 228 –2.35
Maximum – 250 mA >= 23 1.11 239 –2.00
Note: Dynamic TXB is only used in CDMA TX modes. For AMPS operation CLY–10 PA
(V113) bias is to draw 100 mA at low output powers. The output power of the AMPS
transmitter increases, the CLY–10 self–biases from the input signal at the gate, thus in-
creasing the current draw to as much as 320 mA.
The negative voltage generator N200 generates the VNEG voltage.
VNEG comes up when VTXS is active. Both VTXS and VNEG maintain
constant voltage levels while on, 4.45 V and –4.10 V respectively. The
node at R203, R204 and R205 will remain fixed at 2.0 V during the
operation of this circuit. This node is an input to the internal op–amp,
which is pin 53 of the CDCONT IC (N201). The base voltage of V201
tracks the VGG voltage.
Temperature Compensation
A thermister (R141) is mounted closely to the final PA stage CLY–10
(V113). The thermister measures the temperature of the power amplifier
and sends the information to the microprocessor via the RFTEMP1 line.
Circuit Description
CDAGCT IC (N100)
The CDMA Automatic Gain Control Transmitter ASIC, or CDAGCT (N100)
generates the AMPS & CDMA RF signals.
The CDAGCT receives the CDMA baseband I & Q signals from the
CDRFI. These two signals exist upon differential lines, TX_I_N/TX_I_P,
and TX_Q_N/TX_Q_P entering the CDAGCT IC at pins 16, 15 and 13, 12
respectively. These signals can be probed with an oscilloscope at any of
the bypass capacitors in series with these four lines. The level will be
approximately 500 mVpp.