Programme’s After Market Services NHD–4 Series Transceivers Chapter 4 System Module Original 11/97
NHD–4 System Module P.A.M.S Technical Documentation CONTENTS Page No Baseband Block Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Signals and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Memory Block . . . . . .
NHD–4 P.A.M.S Technical Documentation System Module 1st IF AMP (V9) and the Diode Switch (V10) . . . . . . . . . . . . . . . . . . . AMPS Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Filter (Z3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDMA Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDMA IF SAW Filter (Z2) . . . . . . . . . . . . . . .
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P.A.M.S NHD–4 System Module Technical Documentation Table 1. Power Block Connections Signal Name Type (continued) Notes VLCD OUT Voltage for LCD on UIF VBATDET OUT Switched VBATT VC OUT Attenuated VCHRGMON CHRG_INT OUT Signal to indicate a Charger has been connected to Phone. MCU Block Table 2.
NHD–4 P.A.M.S Technical Documentation System Module Table 2. MCU Block Connections Signal Name Type (continued) Notes VCHRGMON IN A/D input for monitoring of charging voltage HOOK_RXD2 IN A/D input – Hook indicator (Phone on or off Hook) BTEMP IN A/D input for monitoring Battery temp. RFTEMP IN A/D input for monitoring RFTEMP 1 and 2 temp. BTYPE IN A/D input for monitoring Battery type. RSSI IN A/D input for monitoring RSSI. JCONN IN A/D input for monitoring Accessory type.
P.A.M.S NHD–4 System Module Technical Documentation DSP Block Table 4.
NHD–4 P.A.M.S Technical Documentation System Module CDSB ASIC Block Table 6. CDSB ASIC Block Connections Signal Name XPWR_ RESET XSYS_RESET Type IN Notes Master reset FROM PSL+ 3 OUT System Reset OSC_OUT IN 32KHz Clk input OSC_IN IN 32KHz Clk input CDRFI_SI CDRFI_SO OUT CDRFI Serial Data In IN CDRFI Serial Data Out CDRFI_SEN OUT CDRFI Serial data ENABLE CDRFI_SCLK OUT CDRFI Serial data CLocK CDRFI_9.8M OUT CDRFI 9.8 MHz clock 15.36M_IN IN 15.36MHz Clk IN 9.83M_IN IN 9.
P.A.M.S NHD–4 System Module Technical Documentation Table 6. CDSB ASIC Block Connections Signal Name Type (continued) Notes MCUDA I/O MCU Data Bus XMCU_AS IN MCU Address Strobe XMCU_RD IN MCU Read Enable XMCU_WR IN MCU Write used as Read/Write select MCU_NMI OUT MCU Non Maskable Interupt MCU_INT0 OUT MCU Maskable Interupt 1 MBUS_DET IN MBUS data input. CHRG_INT IN Signal to indicate a Charger has been connected to Phone.
NHD–4 P.A.M.S Technical Documentation System Module Table 6. CDSB ASIC Block Connections Signal Name Type (continued) Notes RF_RFE6 OUT SEL1 RF_RFE7 OUT RF Control Line CDRFI Block Table 7. CDRFI Block Connections Signal Name Type Notes XSYS_RESET IN XRESET SDI IN Serial Data In SDO OUT Serial Data Out SENABLE IN Serial data ENABLE SCLK IN Serial data CLocK 9.8M IN 9.
P.A.M.S NHD–4 System Module Technical Documentation AUDIO Block Table 8. Audio Block Connections Signal Name Type Notes VA2 IN Analog supply voltage 1. Max 80 mA.
NHD–4 P.A.M.S Technical Documentation System Module Table 10. UIF Connector Signal Name (continued) Pin / Conn.
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NHD–4 P.A.M.S Technical Documentation System Module MCU Block The MCU block controls the user interface, link layer, upper layer protocols, some physical layer tasks, and accessories not linked to data services. It also executes service and diagnostics commands and manages the battery. DSP Block The DSPU provides control and signal processing for AMPS and CDMA modes of operation.
P.A.M.S NHD–4 System Module Technical Documentation Audio Block The block consists of audio codec with some peripheral components. The codec includes microphone and earpiece amplifier and all the necessary switches for routing. The controlling of the codec is done by the MCU. The PCM–data comes from and goes to DSPs. The code converts analog voice to digital samples that can be processed by the DSP.
NHD–4 P.A.M.S Technical Documentation System Module Introduction NHD–4 uses the same transmitter to up convert, amplify and filter the analog AMPS and the digital CDMA signals. The key differences between analog and digital transmission are the Power Amplifier (PA) bias levels , attenuation levels of the variable attenuator, and operation of the RF transmitter ASIC (CDAGCT). It is important to keep in mind that the AMPS and CDMA signals are significantly different.
P.A.M.S NHD–4 System Module Technical Documentation The gain of the CDMA transmitter is controlled by two devices, the CDAGCT IC (N100) and the AT–109 variable attenuator (V106). The TX_OFFSET voltage will fall somewhere between 0.0 and 3.15 V, read at C703. This circuit can be found on the CDCONT schematic. The resultant voltage is found at the CDCONT IC (N201) at pin 7. The CDCONT IC interprets this voltage and generates the TX_ICT and TX_IREF currents.
NHD–4 P.A.M.S Technical Documentation System Module The auxiliary AGC can be manually adjusted using the AGC_REF PDM controls found in the Service Software. Below is a table detailing typical voltages of the AGC_REF PDM and VC, referenced against CDMA TX output power.
NHD–4 System Module P.A.M.S Technical Documentation TX PA Bias Control (Dynamic TXB) The TXB PDM is used to tune the PA bias current. This PDM voltage interacts with, VTXS, VNEG and an op–amp internal to the CDCONT IC (N201) to produce VGG. VGG is the negative voltage supply to the gate of the CLY–10 PA (V113). As VGG changes, so does the bias current., and thus the gain. For minimum bias, the 100 mA case the TXB PDM voltage will be approximately 1.50 V, and VGG will be about –2.35 V.
NHD–4 P.A.M.S Technical Documentation System Module Bias voltage to the CDAGCT IC is critical. The bias voltage at pins 6, 14, 17, 20, 21, 26, and 29 should always be approximately 3.9 to 4.0 V. Should it drop to low, or become to great, the CDAGCT IC will not operate properly. A loss of gain may also occur. The VTXT regulator supplies voltage to the CDAGCT IC. VTXT should stay constant at 5.3 V in both AMPS and CDMA operation.
NHD–4 System Module P.A.M.S Technical Documentation CLY–10 Power Amplifier (V113) For CDMA operation the CLY–10 bias current is increased directly with increasing output power to ensure linear performance. The bias current is controlled by changing the gate voltage. For minimum bias, the 100 mA case, the bias on the gate will be about –2.35 V. For maximum bias, or the 250 mA case, the bias on the gate will be about –2.00 V. The bias voltage on the drain will be approximately 6.
NHD–4 P.A.M.S Technical Documentation System Module Duplexor (Z102) The Duplexor isolates the transmit signal from the receiver path and permits the phone to transmit and receive signals simultaneously (i.e. Full Duplex operation). The Duplexor is a three terminal, dual frequency (RX and TX) bandpass splitter/filter and provides the common antenna connection to the TX and RX circuits. The transmit signal enters the Duplexor at the “TX” port and exits from the “ANT” port.
NHD–4 System Module P.A.M.S Technical Documentation Receiver Functional Description Introduction NHD–4, being a dual mode phone, has essentially two receivers, the analog AMPS and the digital CDMA. These two receivers share a common front end and only become distinct in the IF stage after mixing down to 45 MHz. A diode switch, V10, channels the received signal to the appropriate receiver. It is important to keep in mind that the AMPS and CDMA signals are significantly different.
NHD–4 P.A.M.S Technical Documentation System Module For operation with the LNA ”on”, RF is routed into the first switch, N702 at pin 5. It exits at pin 7 and enters the LNA through L22. After amplification the receive signal leaves the LNA through C98 and enters the second RF switch, N701, at pin 7. The signal exits the second switch through pin 5 and proceeds into the UHF RX SAW (Z1) through C771. Switching control is accomplished at pins 8 and 1 for both switches.
NHD–4 System Module P.A.M.S Technical Documentation Mixer (T1) The mixer is a three port passive Si device. Of the eight pins, five are grounded. The remaining three constitute the RF, LO and IF ports. The received UHF signal enters the mixer at pin 5, the LO port, from C41. The RX_LO signal originates from the UHF synthesizer and enters the mixer at pin 8, the RF port, via a microstrip line which runs within the PCB, under the components on the board.
NHD–4 P.A.M.S Technical Documentation System Module AMPS Receiver Crystal Filter (Z3) The 45 MHz AMPS RX IF signal routes through the diode switch and is filtered by Z3, the crystal filter. L15, C83, C84 and R29 provide matching and attenuation into the filter. The filtered signal exiting the crystal proceeds through C14 and into the AMPS RX IC, D1 at pin 16. AMPS RX IC (D1) The AMPS RX IC, D1 completes the demodulation of the AMPS signal with the help of some peripheral circuitry.
NHD–4 System Module P.A.M.S Technical Documentation CDMA Receiver CDMA IF SAW Filter (Z2) For CDMA RX operation the 45 MHz IF signal exits the 1st IF amplifier (V9) through pin 4 of the diode switch (V10). This signal then enters the CDMA SAW Filter (Z2), passing through an impedance matching network comprised of L8, L9, C71, C72, and C73. R22 and R23 supply current to V9 and V10. R22 also serves to set the Q of L8. The SAW filter itself has a bandwidth of 1.23 MHz.
NHD–4 P.A.M.S Technical Documentation System Module Either of these two signals can be viewed with an oscilloscope. With an RF input of 881.62 MHz CW into a CDMA receiver tuned to channel 384, either of these signals will appear as sine waves of approximately 190 mVpp magnitude, 100 kHz in frequency. BFILCT (N2) The BFILCT IC, N2 serves to filter the demodulated baseband I & Q signals before delivering them to the CDRFI IC (N700) for A/D conversion. This IC also amplifies the I & Q signals.
NHD–4 System Module P.A.M.S Technical Documentation Synthesizer Functional Description Introduction The synthesizer module generates the oscillations necessary for the operation of the phone. It provides the clock signal for digital ICs and it creates the UHF and VHF oscillations needed to up convert and down convert the baseband signals to RF frequencies. There are three synthesizers in the NHD–4 phone. Only two will be discussed here, the UHF and 180 MHz VHF. The third, a 9.
NHD–4 P.A.M.S Technical Documentation System Module N704 is biased at pin 3 by approximately 3.40 V, supplied from VRX via R803. VRX should be about 4.40 V. The RX_LO signal is routed to the mixer (Z1) through a SAW filter (Z701). N705 is biased at pin 3 to approximately 2.70 V, from VTXT through R809 and R815. VTXT should be approximately 4.40 V. The TX_LO signal is delivered to the CDAGCT IC (N100) pin 2, through C795.
NHD–4 System Module P.A.M.S Technical Documentation AGC Functional Description Signal Descriptions Below are descriptions of the signals found within the CDCONT circuitry. 9.8304 MHz The 9.8304 MHz line is the output of the synthesizer onboard the CDCONT IC (N201). Measured at C217 this signal should be approximately 700 mV when measured with an oscilloscope and a high impedance scope probe. This signal is used to clock the baseband portions of the phone while operating in CDMA mode. 15.36 MHz The 15.
NHD–4 P.A.M.S Technical Documentation System Module RX_ICT RX_ICT is the control current to the CDAGCR IC (N1). RX_IREF RX_IREF is the reference control current to the CDAGCR IC (N1). RX_OFFSET RX_OFFSET is a PDM voltage. CDSB ASIC (D704) pin 123, this PDM will vary from 0 to 3.15 V when moved over its dynamic range. The ASIC side of R712 would be another good probe point. TX_GAIN TX_Gain originates at pin 5 of the CDRFI, and is used for CDMA TX Gain control.
P.A.M.S NHD–4 System Module Technical Documentation VC VC is the control voltage to the AT–109 variable attenuator. VC will typically be about 3.8 V when signaling the AT–109 for minimum attenuation, as it does in AMPS mode operation. VCO_EN VCO_EN is better known as the Reset line. It originates at the CDSB ASIC (D704) pin 128. It terminates at the CDCONT IC (N201) pin 23, the Reset pin.
NHD–4 P.A.M.S Technical Documentation System Module VRX VRX is used to supply the LNA (V12) and the LNA switches (N701, N702). It is also biases the RX_LO gain stage (N704) at the UHF synthesizer module. VRX will be approximately 4.45 V while active in AMPS RX/TX mode. VRXA VRXA is used for AMPS RX applications such as bias for the AMPS RX IC (D1) and the 1st IF gain stage while in AMPS operation. VRXA will be approximately 4.45 V when active. VRXD VRXD will be approximately 4.45 V while active.
NHD–4 System Module P.A.M.S Technical Documentation 9.8304 MHz Synthesizer The CDCONT IC (N201) contains a PLL frequency synthesizer which generates a 9.8304 MHz oscillation used to clock the baseband modules of the phone. The 15.36 MHz VCTCXO is used as the reference oscillation. VRXD_C (VRXD) supply biases the PLL at pin 29 of N201 via R212, decoupled with C221 and C222. There should be approximately 4.15 V on Pin 29.
NHD–4 P.A.M.S Technical Documentation System Module Parts List GR1_17A p.n 0200519 EDMS issue 23.
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