User Guide
Table Of Contents
- Pinouts
- BASEBAND FILTER (N2) IF + FM DETECTOR (D1)
- x SYNTH (N300)
- CDAGCR (N1)
- MCU (D706)
- MCU
- MCU memory Flash (D709), EEPROM (D703), SRAM (D700)
- FLASFM D709 1Mx8
- D703 EEPROM 32kx8 D700 SRAM 32kx8
- DSP memory (D707)
- D707 SRAM 64kx16
- PSL + (N500)
- CDAGCT4 (N100)
- CDCONT5 (N201)
- CDRFI (N700)
- CDSB 4.5 (D704)
- AUDIO CODEC (N600)
- DSP (D705)
- DSP CI5
- BACK TO CONTENTS
PAMS
Technical Documentation
NHD–4
Schematics/Layouts & Pinouts
Page 5–9
Original 11/97
CDCONT5 (N201)
1
3
4
6
5
7
8
9
10
11
12
13
14
15
16
2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
NC
NC
NC
NC
RX_Exp
TX_Exp
Ana_GND
Vref
Vrx90
Vrxs
VRF
Vrx
Vbbf_Pnp_B
Vbbfil
TXFM_Cap
TXI_Ref
TXI
NC
Dig_GND
Reset
TX_Punc
Dig_GND
Rfe2
Rfe1
Rfe0
VPLL_Vrxs by–pass
CHP_GND
VCO_Vrxd by–pass
VCO_Cap_B
VCO_Cap_A
Sub_GND
Vcxo
VCO_in
CHP_Out
VCO_GND
VCO_GND
CLK
VCO_GND
Vtxs
Vrxd
Vrxa
VRF
Vtx_Pnp_B
Vtx
TX_Driver
TX_Cntrl
TX_Level
Vtx
Ana_GND
TX_Driver
NC
NC
TX_Ict
TX_Iref
NC
RX_Iref
RX_Ict
Lim_Adj
NC
NC
NC
CDCONT5
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
9
17
18
19
20
21
22
23
25
24
26
27
28
29
30
31
32
Digital control bit for Regulator switching
Digital control bit for Regulator switching
Digital control bit for Regulator switching
Digital Groung
Digital control bit for Regulator switching
Digital control bit for Regulator switching
Vrxd by–passed supply for PLL digital logic
Ground for Charge Pump circuit
Digital Groung
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
Transmitter power–level information
Reference input to Error Amp.
Switch output
NC
NC
NO CONNECTION
Input to RX Multiplier from RX_dB
Inpur to TX Multiplier from TX_dB
Analog Ground
Reference voltage output
Regulated voltage for the 90 MHz Frequency
Battery voltage supply
Regulated voltage for the BBFIL
Pin for external PNP Base connection for Vbbfil
Regulated Voltage for Chrystal Osc and internal Decode logic
Regulated Voltage for the Receiver RF Circuits
Vrxd by–passed supply for VCO and Clock Buffer
Pin for VCO capacitor
33
34
35
36
37
38
39
40
41
42
44
45
46
47
48
43
Pin for VCO capacitor
Substarate Groung
15.36 MHz clock reference
VCO Ground
Charge Pump Output
VCO input from CHP_Out
9.8304 MHz clock output
VCO Ground
VCO Ground
Regulated Voltage for the AMPS circuits
Regulated Voltage for the TX LO buffer
Battery voltage supply
Regulated Voltage for the AGC circuits CDAGCR & CDCONT
Pin for external PNP Base connection for Vtx
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Regulated voltage for the Transmitter circuits and CDAGCT (Pin 47)
Output of Driver for Power Amp.
Negative input of the Driver circuit for Power Amp. (Pin 48)
Analog Ground
Control current for CDAGCT
NO CONNECTION
NO CONNECTION
Reference current for CDAGCT
NO CONNECTION
NO CONNECTION
NO CONNECTION
Control current for CDAGCR
Reference current for CDAGCR
NO CONNECTION
Indicator for Limiter
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION