User Guide

PAMS
Technical Documentation
NHD–4
Schematics/Layouts & Pinouts
Page 5–7
Original 11/97
DSP memory (D707)
D707 SRAM 64kx16
1 2 3 4 5 6 7 8 9 10111213141516171819202122
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
PSL + (N500)
PSL
1
2
3
4
5
6
7
8
9
10
11
1213
14
15
16
17
18
19
20
21
22
23
24 VREF
VA1
VL1B
VL1lVL2l
VL3l
XRESET
VBAT1VBAT2
GND
GND
GND
GND
XPWROFF
XPWRON
CHRGDET
DETINCpor
Coff
Creset
VL3B
VL2B
VBATSW
VA2
names beginning with X indicate NOTE:
ACTIVE LOW operation
XPWRON input has internal pull–up resistor
XPPWROFF input has internal pull–down resistor
1 VREF Voltage REFerence output (5mA, ”2%
2 Analog voltage output
3 Base current supply for external transistor (VL1)
4 Output voltage sense from external transistor (VL1)
5 VBATTERY battery voltage
6 Ground (analog/logic)
7 Ground (analog/logic)
8 XPWR_RESET reset control signal to ASIC
9 XPWROFF control input from the MCU
10 XPWRON power on control from UI
11 Battery CHaRGer DETection
12 DETection INput for the supply voltage monitored
13 Connection for an external Capasitor for controlled
Power–ON master Reset
14 Connection for an external timing Capasitor defining
Power–OFF delay
15 Connection for an external timing Capasitor defining
Reset signal delay
16 Output voltage sense from external transistor (VL3)
17 Base current supply for external transistor (VL3)
18 Ground (analog/logic)
19 Ground (analog/logic)
20 Battery Voltage
21 Output voltage sense from external transistor (VL2)
22 Base current supply for external transistor (VL2)
23 VBATDET SWitched VBAT voltage
24 VA2 Analog voltage output (80mA)