User Guide

PAMS
Technical Documentation
NHD–4
Schematics/Layouts & Pinouts
Page 5–4
Original 11/97
CDAGCR (N1)
1
3
4
6
5
7
8
9
11 12 13 14 15 16
2
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32
10
N1
1 GROUND (Return for CCGA stage 3)
3 DC power for CCGA stage 2
2 GROUND (Return for CCGA stage 2)
4 DC power for CCGA stage 1
5 GROUND (Return for CCGA stage 1)
6 180° IF Input
8 Emitters of QC’s
9 Collector’s of Q1
7 GROUND (Return for LNA)
10 Sets bias current for the internal LNA (short=6.2mA)
11 Emitters of Q1 (Internal LNA)
12 Bypass for LNA’s bias line
13 DC power for LNA
14 DC power for gain control
15 GROUND (Return for Gain control)
16 Bypass for CCGA’s conrtol line
17 Bypass for CCGA’s conrtol line
18 180° Clock Input
19 0° Clock Input
20 DC power for LO circuitry
21 GROUND (Return for LO circuitry)
22 GROUND (Return for DeMod circuitry)
23 Input control current reference
24 Input control current
25 DC Power for DeMod circuitry
26 Baseband 90° output
27 Baseband 0° output
28 Set high for –14 dB change in total gain
29 Set high for –7 dB change in total gain
30 GROUND (Return for Outputs Buffers)
31 DC power for Output Buffers
32 DC power for CCGA stage 3
GND4
GND3
VCC3
VCC2
GND2
IFN
GND1
N4
C IF E LNA_BP VCC1 VCC5 GND5 VC
VCN
4LON
4LO
VCC8
GND8
GND6
IREF
ICTL
VCC6
Q
I
SEL1 SEL0
GND7 VCC7 VCC4