User Guide

PAMS
Technical Documentation
NHD–4
Schematics/Layouts & Pinouts
Page 5–12
Original 11/97
36 32.768Khz Clock osc. circuit
37 32.768Khz Clock osc. circuit
44 VL1
Tx power greater than that set by TXI_REF
No Connection
45 GND
46 Connected to VL
55 DBUS Line in
59 No Connection
61 GND
62 Connected to VL1
65 VL1
66 GND
67
74 VL1
75 GND
76 No Connction
87 No Connection
88 VL1
89 GND
90 Connected to GND
91
95
97 No Connection
99 No Connection
103 VL!
105 GND
106 No Connection
109 VL1
110 GND
113 No Connection
117 VL1
118 GND
122 TXB PDM output signal
124 Sleep Clock
126 TXI_REF PDM output signal
131 Connected to GND
132 VL1
146 VL1
148 GND
151 VL1
152 GND
161 VL1
163 GND
176 VL1
No Connection
133 GND
1 GND
2 XPWR_RESET Power on Reset
3 XDSP_STRB DSP External memory strobe
4 DSP_RXW DSP Write enable
5 XDSP_DS DSP data select
6–8 DSPAD DSP Lower address
9 DSP_MCLK DBUS 512KHz Clock
10 DSP_CLK DSP Interrupt request 0
11 DSP_CLK DSP Interrupt request 1
12 RX_FIL_CAL Output soursing rfRX_FIl _CAL
signal
13 VL1
14 DSP_CLK DSP clock output 15.36MHz
15 GND
16–21 DSPAD DSP Lower address
22 VL1
23 GND
24–25 DSPAD DSP Upper address
26 DSPDA DSP data bus
27 VL1
28 No Connection
29–35 DSPDA DSP data bus
38–42 LCD_COL GPIO port 1
43 No Connection
47–52 LCD_COL GPIO port 1
53 CODEC_MCLK Codec clock 512KHz
54 CODEC_FS Codec Sync 8KHz
56 XMCU_WR MCU Write enable
57 XROM_CS ROM select bit
63 MBUSDET Mbus activity detect
68–73 MCUAD MCU Lower address bus
77–84 MCUDA MCU Data bus
85 XSRAM SRAM select bit
86 XMCU_AS MCU Address valid strobe
92 CHRG_INT Charg interrupt
93 CDRFI_GATE Signal to control Transmitt
mode with in CDRFI
94 SWAGC Signal to control gain switching
96 MCUAD MCU Upper address bus
98 MCU_NMI Non Maskable interrupt
100–102 MCUAD MCU Upper address bus
104 MCU_CLK Clock output 15.36MHz
107 XFLASH_CS Flash select bit
108 No Connection
111 DSP_SYNC DBUS 8KHz Sync Clock
112 Connected to GND
114 RX_CAL Output sourcing rfRX_CAL signal
115 AGC_REF Auxilliary AGC PDM
116 TX_SLOPE PDM
119 RX_SLOPE PDM
120 TX_OFFSET PDM
123 RX_OFFSET PDM
125 Connected to VL1
127 AFC PDM output signal
128 VCO_EN VCTCXO enable
129 TX_PUNC Signal to turn off TX
130 XMCU_RD Read enable
134 RF_RFEN2 Power control to CDCONT
135 FAST Output sourcing rfFast signal
136,137 RXI_ Receive I data
138–142 RXQ Receive Q data
143–145 RXI_ Receive I data
147 15.36M_IN Clock
149 RFEN1 Power control to CDCONT
150 RFEN0 Power control to CDCONT
153–160 TXD_ Multiplexed Tx I/Q data in dig mode
Bidirectional transfer of data in dig mode
162 9.83M_IN Clock
164 CDRFI_IQSEL IQ select signal in dig mode
Address select bit in anal mode
165 DAFOUT Analog mode input data
166 CDRFI__SI Serial data output pin
167 CDRFI__S0 Serial data input pin
168 XSYS_RESET System reset signal
169 CDRFI__SEN Serial data enable
170 CDRFI_RWSEL Read/Write select in anal mode
171 CDRFI_SCLK Serial data clock
172 RX_LE RX Synthesizer enable
173 DATA RX Synthesizer serial data
174 CLK Synthesizer serial clock
175 CDRFI_9.8M Clock
58 No Connection
60 VL!
49–52 GPO port 0
48 GPIO Port 1
ASIC CDSB 4.5