User Guide

PAMS
Technical Documentation
NHD–4
Schematics/Layouts & Pinouts
Page 5–10
Original 11/97
CDRFI (N700)
1
3
4
6
5
7
8
9
10
11
12
13
14
15
16
2
17 18 19 20
21 22 23 24 25 26 27 28 29 30 31 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
VCLKIN
VDDD5
CLKIN
ANATX
TXI+
VDDA1
RXAGC1
VDDA2
VREFP
RXQ
RXI
VSSA2
VREF
TEST
VSSA3
TXI –
VDDA3+4
TXQ+ TXQ –
VSSA4
ANARX+DAF
VSSD1
DAFOUT
SDI SDO
XRESET
SENABLE
R/WSEL
SCLK
VDDD1
VDDD2
IQSELECT
TDX0
TDX3
TDX2
TDX1
TDX4
TDX5
TDX6
EXTTXENA
9.8M
TDX7
VSSD2
VSSD3
EXTVCLKEN
RXI0
RXI1 RXI3 RXI2 RXI4 RXI5
RXQ0 RXQ1
RXQ2 RXQ3 RXQ4 RXQ5 VDDD3 CLKOUT VDDD4
VCLKOUT
VSSD4
CDRFI
TXAGC1
VSSA
1
1 15.36MHz VCLock recovery INput
2 Digital Power VL3
3 9.83MHz CLock recovery INput
4 Analog Ground
5 TX_GAIN TX AGC control
6 Analog Power VL3
7 RX_GAIN RX AGC control
8 Analog Power VL3
9 Positive Voltage REFerence bypass
10 RX_Q RX signal Quadrature–phase
11 Analog Ground
12 Voltage REFerence bypass
13 RX_I RX signal In–phase
14 TEST input (Not used)
15 Analog Ground
16 MOD ANAlog mode TX signal
17 TX_I_P TX signal In–phase +
18 TX_I_N TX signal In–phase –
19 Analog Power VL3
20 TX_Q_P TX signal Quadrature–phase +
21 TX_Q_N TX signal Quadrature–phase –
22 Analog Ground
23 DAF ANAlog mode RX+DAF signal
24 Analog Ground
25 DAF OUTput
26 CDRFI_SI Serial data In
27 CDRFI_SO Serial data Out
28 XSYS_RESET Whwen set = 0
29 CDRFI_SEN Serial data ENABLE
30 CDRFI_RWSEL Read/Write SELect
31 CDRFI_SCLK Serial data CLock
32 Digital Power VL3
33 Digital Power VL3
34 CDRFI_IQSEL TX IQ SELECT
35–42 TXD TX Data bit 0–7
43 CDRFI_GATE EXTernal TX ENAble
44 Digital Ground
45 CDRFI_9.8MHz clock
47 VCO_EN EXTernal VCLK ENAble
48 No Connection
46 Digital Ground
49–53 RXI RX In–phase data bit 1–5
55–59 RXQ RX Quadrature–phase data bit 1–5
60 Digital Power VL3
61 9.38M_IN CLocK recovery OUTput
62 Digital Power VL3
63 V15.36M_IN CLocK recovery OUTput
64 Digital ground
54 No Connection
VERSION 6.0