Programme’s After Market Services NHD–4 Series Transceivers Chapter 5 Schematics/Layouts & Pinouts Original 11/97
NHD–4 PAMS Schematics/Layouts & Pinouts Technical Documentation CONTENTS Page No Pinouts BASEBAND FILTER IF + FM DETECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 x SYNTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDAGCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts BASEBAND FILTER (N2) IF + FM DETECTOR (D1) BASEBAND FILTER N2 11 12 13 14 15 16 17 18 19 20 Q_A33 NC Q_AAFI NC AVDD AGND AVSS NC NC I_AAFI N2 10 9 8 7 6 5 4 3 2 1 I_A33 NC CAL DVDD MC DVSS PD XPD NC Q_PFO 1 2 3 4 5 6 7 8 9 10 Capacitor Input (I–channel) RXI Output (I–channel) RX_FIL_CAL CALlibration start Digital VDD 9.
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts VCN 4LON 4LO VCC8 GND8 GND6 IREF ICTL 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 N4 GND1 IFN GND2 VCC2 VCC3 GND3 GND4 VCC6 Q I SEL1 SEL0 GND7 VCC7 VCC4 25 26 27 28 29 30 31 32 N1 10 9 16 15 14 13 12 11 VC GND5 VCC5 VCC1 LNA_BP E IF C CDAGCR (N1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GROUND (Return for CCGA stage 3) GROUND (Return for CCGA stage 2) DC power for CCGA stage 2 DC power for CCGA stage 1 GROUND (Return for CCGA stage 1)
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts MCU (D706) NC NC RD WR Vcc MD0 MD1 MD2 STBY RES NMI Vss D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 No Connection 2 No Connection 3 MCUREAD : Goes Low to indicate that the CPU is reading external address 4 MCU_WR : Goes Low to indicate that the CPU is writing external address 5 Power VL1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts MCU memory Flash (D709), EEPROM (D703), SRAM (D700) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FLASFM D709 1Mx8 D700 SRAM 32kx8 Page 5–6 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 D703 EEPROM 32kx8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Original 11/97
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts DSP memory (D707) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 D707 SRAM 64kx16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PSL + (N500) Cpor Coff Creset VL3l VL3B GND GND VBAT2 VL2l VL2B VBATSW VA2 13 14 15 16 17 18 19 20 21 22 23 24 PSL 12 11 10 9 8 7 6 5 4 3 2 1 DETIN CHRGDET XPWRON XPWROFF XRESET GND GND VBAT1 VL1l VL1B VA1 VREF NOTE: names beginning with X indicate ACTIVE
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts 24 23 22 21 20 19 18 17 ICT GND2C GND2B VPS2B VPS2A GND2A GND4 VPS4 CDAGCT4 (N100) N100 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 25 26 27 28 29 30 31 32 I IN VPS1S QN Q GND4 GND1 MODE LORFN LORF GND3 PD GND1 VPS1 LOIFN LOIF IREF VPS2C GND2D GND3 VPS3 BRF RFNOUT RFOUT 1 180° LO for RF Mixer (Ground with cap) 2 TX_LO 0° LO for RF Mixer 3 GROUND (Return for RF Mixer and Power Amp) 4 TX_PUNC Control for active/power–down modes 17 DC Pow
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC NC NC Lim_Adj RX_Ict RX_Iref NC TX_Iref TX_Ict NC NC TX_Driver Ana_GND TX_Level Vtx TX_Cntrl CDCONT5 (N201) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CDCONT5 TX_Driver Vtx Vtx_Pnp_B Vrxd VRF Vtxs Vrxa VCO_GND CLK VCO_GND VCO_in CHP_Out VCO_GND Vcxo Sub_GND VCO_Cap_A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC TXFM_Cap TXI_Ref TXI NC Dig_GND Reset TX_Punc Dig_GND Rfe2 Rfe1 Rfe0 VPL
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VSSD4 VCLKOUT VDDD4 CLKOUT VDDD3 RXQ5 RXQ4 RXQ3 RXQ2 RXQ1 RXQ0 RXI5 RXI4 RXI3 RXI2 RXI1 CDRFI (N700) VCLKIN VDDD5 CLKIN VSSA 1 TXAGC1 CDRFI VERSION 6.0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RXI0 EXTVCLKEN VSSD3 9.
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts 90 89 92 91 94 93 95 96 99 97 100 33 34 98 102 43 44 41 42 39 38 37 36 35 40 103 104 105 106 107 108 109 110 112 111 113 115 114 116 117 118 119 121 120 122 123 124 125 127 126 128 129 VSSext tmPurX dspStorobeX dspReadWriteX dspDsx dspAddrL_3 dspAddrL_2 dspAddrU_14 cdDClk cdint1X cdint2X cdRfe_4 VDDint cdDspClk VSSint dspAddrL_1 dspAddrL_4 dspAddrL_5 dspAddrL_6 dspAddrL_7 dspAddrL_0 VDDext VSSex
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts ASIC CDSB 4.
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts AUDIO CODEC (N600) VL1 CDO DX GND FS MCLK LO MIC2N MIC2P MIC1N MIC1P GND MIC3N MIC3P 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CODEC 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BZ CI CS CCCLK DR GND VLRP VLRN VFEARP VFEANR NC VA2 VA2 NC 1 Not connected 2 VA2 Power supply for the analog section 3 VA2 Power input for power section 4 Not connected 5 Not connected 6 XEAR_HFJPWR External earpiece output VF+ 7 EarN Differential / earpiece amp outputs 8
NHD–4 PAMS Technical Documentation Schematics/Layouts & Pinouts DSP (D705) CVSS A10 A11 A12 A13 A14 A15 CVDD CVSS CVSS CVDD READY PS DS IS R/W MSTRB IOSTRB MSC XF HOLDA IAQ HOLD BIO MP/MC DVSS CLKR0 CLKR1 FSR0 FSR1 DR0 DR1 CLKX0 CLKX1 CVSS CVDD FSX0 FSX1 DVDD DVSS DX0 DX1 IACK / NMI / INT0 / INT1 / INT2 / INT3 CVDD CVSS Page 5–14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DSP CI5 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DVDD DVSS CVSS CVDD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D
