Programme’s After Market Services NHP–4 Series Transceivers Chapter 4 System Module Issue 1 04/99
NHP–4 System Module PAMS Technical Documentation Contents Page No Baseband Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband Block Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Signals and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . .
NHP–4 PAMS Technical Documentation System Module List Of Figures Page No Figure 1 Baseband – Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4 DSP memory configuration w/ 64k external SRAM . . . . . . . . . . RF/BB Block Diagram . . . . . . . . . . .
NHP–4 System Module PAMS Technical Documentation This page intentionally left blank Page 4–4 Issue 1 04/99
NHP–4 PAMS Technical Documentation System Module Baseband Block Baseband architecture refers to all those technology elements in the phone design which do not include the RF functions. This document describes in overview, the HD891 baseband architecture. Primarily the focus of this document will be to highlight those aspects of the baseband architecture which are unique to the CDMA project.
PAMS NHP–4 System Module Technical Documentation Internal Signals and Connections Power Block Table 1. Power Block Connections Signal Name Type Notes To/From XPWRON IN Power on switch UIF WATCHDOG IN Watchdog reset pulse MCU VBATTERY IN Battery voltage Sys. conn. CHAR+ IN Charger Voltage Sys. conn. CHAR– IN Charger Return GND CHAR_PWM IN PWM for controlling battery charging MCU XPWR_RESET OUT Master reset, Power–on Reset ASIC 3VA OUT Analog 3.
NHP–4 PAMS Technical Documentation System Module Table 2. MCU Block Connections Signal Name XCODEC_CS CODEC_DO Type (continued) Notes OUT Audio codec chip select IN Audio codec control data To/From MCU MCU CALL_LED OUT UIF CALL_LED enable UIF BACK_LIGHT OUT UIF BACK_LIGHT enable UIF PHFS_TXD2 OUT Hands Free speaker Mute Control and Trans- Sys. conn. mitted data from Flash during Flash Programming. HOOK_RXD2 OUT Recieved data during Flash Programming. Sys. conn.
PAMS NHP–4 System Module Technical Documentation MCU Memory Block Table 3. MCU Memory Block Connections Signal Name Type Notes To/From MCUAD(19:0) IN MCU 20 bit Address Bus MCU MCUDA(7:0) I/O MCU 8 bit Data Bus MCU XMCU_RD IN MCU Read used as Output Enable MCU XMCU_WR IN MCU Write used as Read/Write select MCU XFLASH_CS IN Flash Chip Select ASIC XSRAM_CS IN SRAM Chip Select ASIC VF IN 12 volt line for Flash programming Sys. conn. DSP Block Table 4.
NHP–4 PAMS Technical Documentation System Module DSP memory Block Table 5. DSP Memory Block Connections Signal Name Type Notes To/From DSPAD(15:0) IN DSP 16 bit Address Bus DSP DSPDA(15:0) I/O DSP 16 bit Data Bus DSP DSP_RXW IN DSP Read / Write Select DSP XDSP_CS IN DSP SRAM Chip Select for Memory Access CDSB ASIC Block Table 6.
PAMS NHP–4 System Module Technical Documentation Table 6. CDSB ASIC Block Connections Signal Name Type (continued) Notes To/From DSP_CLK OUT 15.
NHP–4 PAMS Technical Documentation System Module Table 6. CDSB ASIC Block Connections Signal Name Type (continued) Notes To/From RF_SDATA OUT Serial Data RF RF_RX_LE OUT Latch Enable for Serial Data RF RF_TXB OUT Tx Power Bias 8bit PDM – 3.84Mhz RF RF_TXREF OUT REF Level for TXIP comparator 8bit PDM – 1.92Mhz RF RF_AFC OUT VCTCXO control voltage 8bit PDM – 3.840Mhz RF RF_AGCREF OUT AUXAGC RF RF_TXGAIN OUT Offsets TX gain to RX gain –NOT USED HD891– 7bit PDM – 4.
PAMS NHP–4 System Module Technical Documentation CDRFI Block Table 7. CDRFI Block Connections Signal Name Type XSYS_RESET IN XRESET When set = 0, reset registers to default values. ASIC SDI IN Serial Data In ASIC SDO Notes OUT Serial Data Out To/From ASIC SENABLE IN Serial data ENABLE ASIC SCLK IN Serial data CLocK ASIC 9.8M IN 9.
NHP–4 PAMS Technical Documentation System Module AUDIO Block Table 8. Audio Block Connections Signal Name Type Notes To/From 3VA IN Analog supply voltage, Max 80 mA. PWR PCMIN IN Received audio serial data DSP CODEC_FS IN 8kHz frame sync ASIC CODEC_MCLK IN 512kHz codec audio data clock ASIC CODEC_DIN IN Audio codec control data MCU CODEC_CLK IN MCU Clock for audio codec control data transfer XCODEC_CS IN Audio codec chip select MCU XMIC_JCONN IN External microphone Sys.
PAMS NHP–4 System Module Technical Documentation Power Management This section covers the power management system of the HD891 transceiver. The power management software is the same as HD881 with some minor updates, however, the power supply section is completely new. A highly efficient and low noise DC–DC converter is used for most of the baseband power, and the PSL logic is replaced using a few comparators. The charging circuit is also new.
NHP–4 PAMS Technical Documentation System Module Charging Switch/Regulator The charging switch/regulator acts to connect the charger input to the battery with minimal losses. To prevent overcharging the output voltage is limited to 8.4V (+/–0.25V) when CHAR_PWM is high or 5.4V when CHAR_PWM is low (startup). Maximum current is 1000mA. The input is protected against transients by a varistor. Maximum dc input voltage range is –5V to +16V. Charging is controlled by the CHAR_PWM signal.
PAMS NHP–4 System Module Technical Documentation DC–DC Converter, Regulators, Reset The main 3VD supply for baseband is regulated by a DC–DC converter. It offers 90% efficiency in normal mode and 80% during sleep. The free–run operating frequency is 250kHz, but locks to either 307kHz (CDMA) or 340kHz (AMPS) of the PWR_CLK input signal (Note: HD891 will operate in CDMA mode only). The PLL lock time is 10ms. To put the DC–DC converter into sleep mode the shutdown pin and PWR_CLK should be held low.
NHP–4 PAMS Technical Documentation System Module External Memory External memory accessed by the MCU: 1M x 8bit FLASH memory – 150 ns maximum read access time – contains the main program code for the MCU ; in the beginning the DSP program code locates also in FLASH – Not all the FLASH is used, ONLY 40000 and up is available.
NHP–4 System Module PAMS Technical Documentation MBUS MBUS interface will be implemented via serial port on the MCU. Protocol will be DCT MBUS compatible. DSP Block The DSP block functions include speech processing, time critical physical layer tasks, and multiplex sublayer tasks. The block consists of a TI LEAD processor clocked by the 15.36 Mhz system clock. An internal upconverter and PLL mechanism in the DSP will allow machine cycle rates up to 50 MHz.
NHP–4 PAMS Technical Documentation System Module External Memory 64k x 16 SRAM memory – 85 ns maximum read access time Figure 4 shows the relative location and sizes of the memories used in the program and data spaces of the processor with 64k external SRAM.
NHP–4 System Module PAMS Technical Documentation Multipath Analyzer The Nokia Multipath Analyzer (MA) consists of several Microsoft Windows application programs running on a PC with a PC DSP card that will receive (only) real–time information from the DBUS. The Clock will be provided by the PC DSP card. The DSP will send, selected by a test bitmask, through its built–in serial port, test data to be processed by the MA’s PC DSP card.
NHP–4 PAMS Technical Documentation System Module The DSP can modify the RFIPDMSRC(4:0) register to allow the DSP algorithms to control the cdAfc, cdTxb, cdTxc, cdTxGainAdj and cdAgcRef. All PDM outputs can be inverted by modifying the RFPDMPOL(2:0) and RFPDMPOL(4:0) registers. CDRFI CDRFI is a monolithic CMOS high speed CODEC designed for use in CDMA (Code Division Multiple Access) Digital Cellular Telephone applications.
NHP–4 System Module PAMS Technical Documentation – Digital control: – 12 bit bus for signal ADC’s. – 8 bit bus for signal DAC’s and analog mode signal converters. – Serial bus for AGC DAC’s. – Clock recovery circuits (input signal level 200 mVrms sinewave, output 3volt–level): – 9.8304 MHz squaring circuit. –15.360 MHz squaring circuit. Audio Block The block consists of audio codec with some peripheral components.
NHP–4 PAMS Technical Documentation System Module RF Block Introduction This document is divided into three major sections of the RF circuitry: the transmitter, the receiver, and the synthesizer. Transmitter Functional Description The 2170 uses CDMA spread spectrum modulation producing a channel bandwidth of 1.23 MHz. For any transmit output level, the power is spread over the entire channel bandwidth. The transmitter frequencies are 1850 to 1910 MHz.
NHP–4 System Module PAMS Technical Documentation The TX Gain is designed to overcome gain variation across the band as well as device–to–device variations. Therefore, it is possible (using manual control when transmit limiting is off) to produce an output power that causes the phone to produce power much higher than necessary resulting in excessive heat. If left on even for a few minutes without current limiting the power supply, the unit can be damaged.
NHP–4 PAMS Technical Documentation System Module CDMA TX Gain Control A fundamental requirement for proper CDMA system operation is that received signal power levels reaching the digital demodulators remain constant. This is true for both the mobile unit and the base station. The mobile unit must dynamically adjust the gain of its receiver to ensure that the down converted baseband I & Q signal levels delivered to the CDSB ASIC are always constant.
PAMS NHP–4 System Module Technical Documentation The TX_IF_AGC voltage is then fed into an op–amp level shifter circuit (N302) which outputs the two DC level–shifted output signals which control the IF AGC IC (N308) and the RF AGC AT–118 attenuator (N300) from 0 to 2 V, approx. The TX_AGC_ADJ signal from the CDSB ASIC (N705, Pin 115) is simply used to provide a DC voltage level from which to adjust the slope of the RF AGC attenuator (N300) over the voltage range of the TX_IF_AGC input.
NHP–4 PAMS Technical Documentation System Module Circuit Description IQ Modulator (N307) The I/Q inputs from the baseband contain spread spectrum data with a frequency range of 0 to 615 kHz. These inputs to the modulator are differential (positive and negative inputs), driven from the baseband by the CDRFI (N703). Beginning at the transmitter schematic page, these inputs, labeled TXI+/– and TXQ+/–, are matched to the modulator input load requirements for pins 1–4 of the RF2703 I/Q modulator IC (N307).
NHP–4 System Module PAMS Technical Documentation IF AGC IC (N308) The CDMA Automatic Gain Control Transmitter IC, or Q5505 (N308), provides the gain control at the IF frequency, 208.1 MHz. The range of gain is typically +39 dB to –65 dB which varies from unit to unit for a more reasonable 85 dB total of dynamic range. The typical input signal amplitude of –40 dBm is present at Pin 1 (CDMA+) input from the output of the I/Q modulator.
NHP–4 PAMS Technical Documentation System Module The power supply of the IC (VDD, Pins 1, 8 and 12) is also filtered to prevent any conducted spurious AC signals. This filtering is accomplished by using ‘microstrip’ filters (Z135, Z136) printed on the circuit board, in combination with all other AC bypass capacitors. The power supply for this IC is provided by the V4.8TX (N305), which also helps isolate (filter) the power supply signal from AC spurs.
NHP–4 System Module PAMS Technical Documentation The second gain stage, V303, should be biased the same with approximately 4.2 V on the collector and 0.7 V on the base. The current bias circuit of V308 acts the same as the circuit of V309 for the first stage, except that the bias current is increased slightly by R344 to provide better linearity performance due to the higher RF input power to the amplifier.
NHP–4 PAMS Technical Documentation System Module PA Bias Circuitry (V300) The PA is provided with a constant voltage source at 6.2 V using the FZT749 PNP power transistor (V300). This circuit is devised to provide a constant base bias current, since the collector is set to a constant voltage from the V301 current bias circuit. This circuit is enabled by the V4.8TX (N305) regulator, where the base voltages of both NPN transistors (V301) is set to approx. 2.3 V. This sets the emitter voltages to 2.3 – 0.
NHP–4 System Module PAMS Technical Documentation Thermistor (R307) The thermistor R141 changes resistance as a function of its temperature. The voltage across this device comprises the RFTEMP1 signal to the MCU (D700). It is placed near the power transistor (V300) and the power amplifier (N304) for worst–case board temperature measurements.
NHP–4 PAMS Technical Documentation System Module Receiver Functional Description The 2170 uses a single–mode CDMA receiver, which will downconvert a 1.23 MHz wide signal down to the baseband modulated signal, 615 kHz in bandwidth. The receiver uses a heterodyne deisgn technique where the incoming signal is down converted from the PCS RX Band, 1930 MHz to 1990 MHz, to a fixed IF frequency at 128.1 MHz, filtered, then down converted to it’s quadrature components at baseband.
NHP–4 System Module PAMS Technical Documentation 1st LNA (V1) and Active Bias (V3) The first LNA, V1, provides approximately 14 dB of gain to the RX chain. The current source to this device originates from the active bias circuitry consisting two transistors (V3) providing constant current to V1. The collector current to V1 is mainly controlled by R3 and R15, whereas the base current is controlled by R7. Additionally, R12, and R13 set up the voltage dividing ratio for the voltage bias for V3.
NHP–4 PAMS Technical Documentation System Module The LO_PRX signal originates from the UHF synthesizer and enters the mixer at pin 3, the RF port, through a 3 component matching network (R8, L5, C20). The LO_PRX signal is strong, minimum +4 dBm, and should be present and locked shortly after the ‘SYN_PWR_ON’ signal is turned on. If the locked signal is not present, then it is required to debug the synthesizer. It should always be 128.1 MHz greater in frequency than the received signal.
NHP–4 System Module PAMS Technical Documentation The baseband section uses DSP to determine the amplitude of the incoming I and Q baseband signals. The baseband then controls the RX_IF_AGC voltage to produce the equivalent of –13 dBm (into 50 ohms) at the RX_I and RX_Q signal outputs of the BBFIL (N10). Unlike conventional RF power detection methods, the RSSI (Receive Signal Strength Indicator) is then calculated using DSP from the resulting RX_IF_AGC voltage and the RX_I and RX_Q signal levels.
NHP–4 PAMS Technical Documentation System Module There is a FET switch (V6) that controls the digital control signal, BBFIL_CNTRL. Thus, when the BBFIL_CNTRL is logic high (3.0 V), the BBFILCT (N10) will be on. Additionally, the 9.8304 MHz signal is used by the BBFILCT IC (N10) as its clock, since the IC is a digital filter. If the 9.
NHP–4 System Module PAMS Technical Documentation Synthesizer The synthesizer module generates the oscillations necessary for the operation of the phone. It provides the clock signal for digital ICs and it creates the UHF and VHF oscillations needed to up convert baseband signals to RF frequencies and down convert RF signals to baseband. There are four synthesizers and one frequency multiplier in the 2170 phone all based on the Motorola SEA3 15.36 MHz VCTCXO (G100).
NHP–4 PAMS Technical Documentation System Module The IC is programmed serially using the latch enable Pin 14 (SYN_LE1), data Pin 15 (SYN_DAT), and clock Pin 16 (SYN_CLK) are provided from the CDSB ASIC (D705, BB, Sheet 6). Within the data words, the selector bit is provided to determine which half of the IC is programmed, the TX IF or the RF. The supply voltage, VCC, for the chip (Pins 12 and 5) is provided by 2 separate voltage regulators.
NHP–4 System Module PAMS Technical Documentation The LO_TIF signal level is approx. –15 dBm (referenced to 50 Ohm) at the TX LO modulator matching network. This corresponds to an actual input voltage level of 0.06 Vpp at the input of the TX modulator IC (N307, Pin 13). The 256.2 MHz RX VHF LO (LO_RIF)/Fujitsu Single PLL Frequency Synthesizer IC (N106) This IC provides the internal circuitry for the 256.2 MHz RX VHF (LO_RIF) phase–lock loop.
NHP–4 PAMS Technical Documentation System Module 9.8304 MHz Baseband Clock This signal is created by using the PLL circuitry on the Motorola MC145162D, a passive loop filter (C138, C139, R129, R126, C164), and a discrete VCO (V106, V104). The VCO is powered by V4.8SYN (N100) with the proper bypass filtering for a clean power supply. The output signal is approx. 1 Vpp, and is fed back to the Motorola PLL IC (N102) to complete the loop.
PAMS NHP–4 System Module Technical Documentation Parts List– GR2 _11 p.
NHP–4 PAMS Technical Documentation R112 R113 R114 R115 R116 R117 R118 R119 R120 R121 R122 R123 R124 R125 R126 R127 R128 R129 R130 R131 R132 R133 R134 R135 R136 R137 R138 R139 R140 R141 R142 R143 R144 R145 R146 R147 R148 R149 R150 R151 R152 R153 R154 1430762 1430690 1430700 1430764 1430726 1430758 1430730 1430700 1430784 1430730 1430790 1430716 1430808 1430788 1430764 1430798 1430754 1430754 1430772 1430740 1430804 1430784 1430760 1430726 1430690 1430760 1430690 1430738 1430730 1430710 1430738 1430776 143
PAMS NHP–4 System Module R155 R156 R157 R300 R301 R302 R303 R304 R305 R306 R307 R308 R309 R310 R312 R313 R314 R315 R316 R317 R318 R319 R320 R321 R322 R323 R324 R325 R326 R327 R328 R329 R330 R331 R332 R333 R334 R335 R336 R337 R338 R339 R340 1430746 1430710 1430726 1430766 1430764 1430756 1430754 1430754 1430734 1430754 1800659 1430794 1430770 1430770 1430700 1430754 1430744 1430702 1430744 1430754 1430740 1430708 1430740 1430710 1430740 1430800 1430810 1430840 1430800 1430810 1430800 1430808 1430808 14307
NHP–4 PAMS Technical Documentation R341 R342 R343 R344 R345 R346 R347 R348 R349 R352 R353 R354 R355 R356 R357 R358 R359 R360 R508 R700 R701 R702 R703 R704 R705 R706 R707 R708 R709 R710 R711 R712 R713 R714 R715 R716 R717 R718 R719 R720 R721 R722 R723 1430690 1430700 1430700 1430702 1430756 1430776 1430712 1430754 1430774 1430754 1430742 1430742 1430754 1430772 1430772 1430772 1430772 1430700 1430690 1430700 1430794 1430800 1430770 1430778 1430804 1430804 1430135 1430321 1430317 1430744 1430853 1430804 143
NHP–4 System Module R724 R725 R726 R727 R728 R729 R730 R731 R733 R735 R736 R737 R738 R739 R740 R741 R742 R743 R744 R745 R746 R747 R748 R749 R750 R751 R752 R753 R754 R755 R757 R758 R760 R761 R762 R763 R764 R765 R766 R767 R768 R769 R770 1430820 1430804 1430043 1430800 1430804 1430812 1430820 1430790 1430744 1430700 1430804 1430726 1430726 1430726 1430820 1430800 1430788 1825005 1430788 1430859 1430788 1800659 1430726 1430788 1430804 1430832 1430788 1430778 1430135 1430690 1430820 1430033 1430726 1430726 143
NHP–4 PAMS Technical Documentation R771 R772 R773 R774 R775 R776 R777 R778 R779 R780 R781 R782 R783 R784 R785 R787 R788 R789 R790 R792 R793 R794 R795 R796 R797 R799 R800 R801 C001 C002 C003 C004 C007 C011 C013 C015 C016 C017 C018 C019 C020 C021 C022 1430726 1430726 1430754 1430778 1430780 1430758 1430690 1430690 1430804 1430792 1430792 1430794 1430804 1430726 1430830 1430848 1430848 1430848 1430848 1430031 1430778 1430738 1430778 1430744 1430744 1430808 1430808 1430700 2320526 2309570 2320620 2610003 232
PAMS NHP–4 System Module C023 C024 C025 C026 C027 C028 C029 C030 C031 C032 C033 C034 C035 C036 C037 C038 C039 C040 C041 C042 C043 C044 C045 C046 C047 C048 C049 C050 C051 C052 C053 C054 C055 C056 C057 C058 C059 C060 C061 C100 C101 C102 C103 2312401 2320604 2320584 2610003 2320620 2309570 2320584 2320540 2320781 2320781 2320540 2320604 2320620 2320584 2320620 2320620 2312401 2320620 2320584 2320604 2310784 2320620 2320620 2320620 2320604 2320560 2320536 2320781 2320781 2320781 2312401 2320540 2320620 23207
NHP–4 PAMS Technical Documentation C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 2320779 2320604 2320548 2320556 2320556 2320604 2320620 2320620 2320538 2320552 2610003 2320620 2320620 2320540 2320620 2320620 2320572 2320620 2320536 2320536 2610003 2320131 2320602 2320620 2312401 2320602 2320596 2320620 2320620 2320604 2320604 2320620 232
PAMS NHP–4 System Module C147 C148 C149 C150 C151 C152 C153 C154 C155 C156 C157 C158 C159 C160 C161 C162 C163 C164 C165 C166 C167 C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 C178 C179 C180 C181 C182 C183 C184 C185 C186 C187 C188 C189 2320620 2320604 2320604 2320781 2320620 2610003 2310784 2320620 2610003 2320620 2610200 2310784 2320604 2309570 2610003 2320604 2320584 2320620 2320620 2320544 2320536 2320558 2320540 2320532 2320779 2320620 2610003 2320604 2320620 2320604 2320524 2320604 2320620 23205
NHP–4 PAMS Technical Documentation C300 C301 C302 C303 C304 C305 C306 C307 C308 C309 C310 C311 C312 C313 C314 C315 C316 C317 C319 C320 C322 C323 C324 C325 C326 C327 C328 C329 C330 C331 C332 C333 C334 C335 C336 C337 C338 C339 C340 C341 C342 C343 C344 2312293 2320538 2320584 2320779 2320584 2320620 2320779 2320518 2320516 2320520 2309570 2320538 2320520 2320604 2320538 2320584 2320584 2320779 2320584 2320538 2320620 2320620 2320560 2320538 2320584 2320538 2320508 2320584 2320530 2320558 2320620 2320620 232
PAMS NHP–4 System Module C345 C346 C347 C348 C349 C350 C351 C352 C353 C354 C355 C356 C357 C358 C359 C360 C361 C362 C363 C364 C365 C366 C367 C368 C369 C370 C371 C372 C373 C374 C375 C376 C377 C378 C379 C380 C381 C382 C383 C384 C385 C386 C387 2320516 2320518 2320620 2320538 2320538 2320584 2320538 2320538 2320560 2320538 2320584 2320584 2320538 2320538 2320620 2309570 2320584 2610003 2310784 2320620 2320538 2320538 2320538 2320584 2310784 2610003 2320534 2320524 2320604 2320620 2320584 2320584 2320620 23205
NHP–4 PAMS Technical Documentation C388 C700 C701 C702 C703 C704 C705 C706 C707 C709 C710 C711 C712 C713 C714 C715 C716 C717 C718 C719 C720 C721 C722 C723 C724 C725 C726 C727 C728 C729 C730 C731 C732 C733 C734 C735 C736 C737 C738 C739 C740 C741 C742 2320538 2320620 2320584 2611675 2320584 2320620 2310003 2310003 2310003 2309570 2310003 2320620 2320560 2320560 2310003 2310003 2320779 2320779 2320620 2310003 2611701 2611701 2320584 2320620 2320584 2320584 2320560 2320620 2310003 2310003 2320620 2320620 231
PAMS NHP–4 System Module C743 C744 C745 C746 C747 C748 C749 C750 C751 C753 C754 C755 C756 C757 C758 C759 C760 C761 C762 C763 C764 C765 C766 C767 C768 C769 C770 C771 C772 C773 C774 C775 C776 C777 C778 C779 C780 C781 C785 C817 C818 C819 C820 2310003 2312403 2320560 2320131 2310003 2320560 2320544 2320584 2320560 2320544 2320620 2320620 2310003 2310003 2310003 2310003 2320584 2310003 2610105 2310003 2320560 2320131 2320781 2320781 2320131 2320131 2320781 2320779 2610003 2312401 2310003 2310003 2320584 23205
NHP–4 PAMS Technical Documentation C821 L001 L002 L003 L004 L005 L006 L007 L008 L009 L010 L011 L012 L013 L014 L034 L100 L101 L102 L103 L104 L105 L106 L107 L108 L109 L110 L111 L300 L301 L302 L303 L304 L700 L701 L702 L703 L704 L705 L706 B700 G100 G101 2312401 3645165 3645101 3645167 3645005 3645165 3645121 3641574 3645163 3645157 3641622 3203701 3608502 3608502 3641620 3641540 3645131 3608502 3608502 3645131 3641622 3608502 3645131 3608407 3608407 3645005 3645121 3645177 3203701 3641574 3203701 3203701 364
NHP–4 System Module Z001 Z002 Z103 Z300 Z301 Z302 Z706 T300 V001 V003 V004 V005 V006 V100 V101 V102 V103 V104 V105 V106 V107 V108 V109 V300 V301 V302 V303 V304 V305 V306 V307 V308 V309 V700 V701 V702 V703 V704 V705 V706 V707 V708 V709 4511027 4512021 4511025 4510173 4550049 4550049 4511027 3640419 4210074 4219908 4210091 4219908 4210021 4110023 4210066 4210066 4210074 4210117 4210100 4110017 4210066 4210074 4110023 4210112 4219912 4211264 4210091 4210052 4210091 4210052 4110078 4219908 4219908 4117993 421
NHP–4 PAMS Technical Documentation V710 V711 V712 V714 V715 V716 V717 V718 D700 D701 D702 D703 D704 D705 D706 D707 D708 D709 N001 N002 N005 N006 N007 N008 N009 N010 N100 N101 N102 N103 N104 N105 N106 N300 N301 N302 N303 N304 N305 N306 N307 N308 N700 4210052 4210050 4210052 4110078 4211264 4117993 4111824 4219912 4370401 4340451 4340219 4340357 4340387 4370375 4340447 4370287 4340149 4340493 4340419 4340407 4340415 4340411 4340041 4340443 4340459 4370291 4340419 4340347 4340467 4340415 4340419 4340413 434
NHP–4 System Module N701 N702 N703 N704 N705 N706 N707 N708 X002 X700 X701 E007 4340363 4340365 4370189 4340371 4340365 4340131 4340419 4340445 9510277 5469035 5431718 9510385 9854233 9854233 Page 4–58 PAMS Technical Documentation IC, op amp +2.7/5/10v sot23 LMC7111 SOT23–5 IC, 2x up voltage comp. tsso TLC393 TSSOP8 Cdma rf frnt–end cdrfi 6.0 TQFP64 Max887 dc/dc conv 3.5–11v SO8 IC, 2x up voltage comp. tsso TLC393 TSSOP8 St5090 audio codec TQFP44 IC, regulator TK11248BMC 4.8 V SOT23L IC, op amp 2.
