User Guide

Table Of Contents

After the blocking filter, the signal is fed into a buffer amplifier, which also has programmable gain. Around

the amplifier there is the first DC-offset compensation block, which removes most of the cumulated DC offset

so far. The DC offset compensation method is based on digital successive approximation technique.

The next block in the RX chain is a switched-capacitor (SC) channel filter, which provides the close-in selectivity

for the analog receiver. Because the SC-filter is insensitive to the IC process tolerances, no production

calibration of the filter is necessary. The SC-filter operates on 6.5 MHz clock, which is generated by dividing

the 26 MHz reference clock by four.

After the SC-filter there is a continuous-time smoothing filter which attenuates the alias signals generated

by the sampling process inherent in the SC-filter. The smoothing filter also has programmable gain.

The next block is a programmable gain amplifier (PGA), which has the second DC-offset compensation block

around it. The DC-offset compensation method is again based on digital successive approximation technique.

The last block in the analog receiver is an output buffer amplifier, which feeds the differential I/Q signals off-

chip to be A/D converted in the digital baseband.

VCXO and PLL

The VCO frequency is locked by a PLL (phase locked loop) into a stable frequency source given by a VCXO. The

frequency of the VCXO is in turn locked into the frequency of the base station with the help of an AFC (automatic

frequency control) voltage, which is generated in the UEM. The reference frequency is 26 MHz.

The VCXO also provides a 26 MHz system clock for the digital baseband.

The PLL is located in PMB3258 and it is controlled via the RFBUS.

RM-394; RM-395; RH-118

System Module

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