User's Manual

Table Of Contents
Verify and Upgrade ROMMON Version – continued
FEB 2005 1X SC 4812T Lite BTS Optimization/ATP I-67
PRELIMINARY
Table I-13: Verify and Replace the Installed ROMMON Version using a TFTP Server
n Step Action
* IMPORTANT
This procedure does not cover all aspects of BTS Router Operation and programming.
Before performing this procedure, review BTS Router initialization, operation, and programming
information and procedures in MWR1941 Wireless Mobile Edge Router Software Configuration
Guide; part number 78–13983–01.
Have this publication available for reference while performing this procedure.
1 This procedure assumes the LMF Computer and BTS Router are configured, connected, and
operating as they would be after performing the procedures in Table I-4, Table I-5, Table I-6, and
Steps 1 through 4 of Table I-7.
If necessary, perform these procedures now.
2 Identify the installed ROMMON Version from the BTS Router Privileged EXEC Mode Prompt:
sh
ow version
A response similar to the following will be displayed:
BTSRTR1#sh ver
Cisco Internetwork Operating System Software
IOS (tm) 1941 Software (MWR1941–I–M), Version 12.2(8)MC2b, EARLY DEPLOYMENT RE-
LEASE SOFTWARE (fc3)
TAC Support: http://www.cisco.com/tac
Copyright (c) 1986–2002 by cisco Systems, Inc.
Compiled Mon 05–Aug–02 11:07 by nmasa
Image text–base: 0x60008940, data–base: 0x60B54000
ROM: System Bootstrap, Version 12.2(20020113:235343) [sbose–wilma 109], DEVELOP-
MENT SOFTWARE
ROM: 1941 Software (MWR1941–I–M), Version 12.2(8)MC2b, EARLY DEPLOYMENT RELEASE
SOFTWARE (fc3)
Router uptime is 1 minute
System returned to ROM by power–on
System image file is ”slot0:mwr1941–i–mz.122–8.MC2b.bin”
cisco mwr1941 (R7000) processor (revision 0.1) with 121856K/18432K bytes of
memory.
Processor board ID JMX0611K5TS
R7000 CPU at 240Mhz, Implementation 39, Rev 3.3, 256KB L2 Cache
Bridging software.
X.25 software, Version 3.0.0.
Primary Rate ISDN software, Version 1.1.
Toaster processor tmc is running.
2 FastEthernet/IEEE 802.3 interface(s)
2 Serial network interface(s)
2 Channelized T1/PRI port(s)
DRAM configuration is 64 bits wide with parity disabled.
55K bytes of non–volatile configuration memory.
31360K bytes of ATA Slot0 CompactFlash (Read/Write)
Configuration register is 0x101
BTSRTR1#
table continued on next page
I