Data Sheet

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Nexperia B.V. 2017. All rights reserved
PHC21025 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 04 — 17 March 2011 2 of 16
Nexperia
PHC21025
Complementary intermediate level FET
[1] Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with a
thermal resistance from ambient to solder point of 90 K/W.
2. Pinning information
3. Ordering information
Dynamic characteristics
Q
GD
gate-drain charge V
GS
=-10V; I
D
=-2.3A;
V
DS
=-15V; T
j
=25°C;
P-channel; see Figure 12
-3-nC
V
GS
=10V; I
D
=2.3A;
V
DS
=15V; T
j
=25°C;
N-channel; see Figure 11
-2.5-nC
Table 1. Quick reference data
…continued
Symbol Parameter Conditions Min Typ Max Unit
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1S1source1
SOT96-1 (SO8)
2 G1 gate1
3S2source2
4 G2 gate2
5D2drain2
6D2drain2
7D1drain1
8D1drain1
4
5
1
8
sym114
D1 D1 D2 D2
S1 G1 S2 G2
Table 3. Ordering information
Type number Package
Name Description Version
PHC21025 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1